| Resume alert | Resumes 11 - 20 of 23 |
Electrical Engineering Customer Service
Fairport, NY, 14450
... built an optical system using interferometry to measure wafer characteristics - Designed an 8 bit ripple carry adder in cadence - Designed and implemented a multi stage amplifier to multiple specifications - Designed and built a solar powered slow ... - 2018 May 15
... built an optical system using interferometry to measure wafer characteristics - Designed an 8 bit ripple carry adder in cadence - Designed and implemented a multi stage amplifier to multiple specifications - Designed and built a solar powered slow ... - 2018 May 15
Knowledge of circuit design principles and high speed timing and SI
Rochester, NY
... Attained an excellent understanding of the Cadence Virtuoso & AMS Designer environments. Coded the testbench and behavioral models using verilog-ams. Insulin Pump ● Served as project manager and technical lead for a custom chip that interfaces with ... - 2018 Apr 10
... Attained an excellent understanding of the Cadence Virtuoso & AMS Designer environments. Coded the testbench and behavioral models using verilog-ams. Insulin Pump ● Served as project manager and technical lead for a custom chip that interfaces with ... - 2018 Apr 10
Electrical engineering, embedded software engineer
Rochester, NY
... Skills Cadence (Analog and Digital design), Silvaco Tools (Deck-build, ATLAS, Athena), Verilog, Embedded C (QNX-Momentix and Freescale), PLC, SCADA, MATLAB, MATLAB Simulink, SPICE, experienced with working in Clean Room, basic knowledge of Perl and ... - 2017 Aug 23
... Skills Cadence (Analog and Digital design), Silvaco Tools (Deck-build, ATLAS, Athena), Verilog, Embedded C (QNX-Momentix and Freescale), PLC, SCADA, MATLAB, MATLAB Simulink, SPICE, experienced with working in Clean Room, basic knowledge of Perl and ... - 2017 Aug 23
Design Electrical Engineering
Rochester, NY
... * **** ********** **** **** and Python 1 Year experience with System Verilog 6 Months experience with CMOS processes 1 Year experience with Full design flow for ASIC/SOC design 1 Year of experience with Cadence EDA /Synopsys tools EDUCATION M.S. ... - 2017 Aug 13
... * **** ********** **** **** and Python 1 Year experience with System Verilog 6 Months experience with CMOS processes 1 Year experience with Full design flow for ASIC/SOC design 1 Year of experience with Cadence EDA /Synopsys tools EDUCATION M.S. ... - 2017 Aug 13
Customer Service Sales
Spencerport, NY, 14559
... PCI, PC/104, ISA Languages: C, C++, VHDL, AHDL, Assembly, Tcl OS: Embedded Linux, Windows, eCos, U-Boot Tools: PADS, Cadence SPECCTRA, Zuken Cadstar, OrCAD, Quartus, ISE, Modelsim, Microsemi Libero, Visual Studio, Code Composer, GNU tools, IAR, ... - 2017 Aug 07
... PCI, PC/104, ISA Languages: C, C++, VHDL, AHDL, Assembly, Tcl OS: Embedded Linux, Windows, eCos, U-Boot Tools: PADS, Cadence SPECCTRA, Zuken Cadstar, OrCAD, Quartus, ISE, Modelsim, Microsemi Libero, Visual Studio, Code Composer, GNU tools, IAR, ... - 2017 Aug 07
Engineer Electrical
Rochester, NY
... Programming Language: C Language, Assembly Language, Verilog, VHDL, PL-SQL Full Custom Chip Design: Cadence Virtuoso and Spectre, Mentor Graphics Pyxis. Publication Submitted Research paper in SOCC IEEE conference “A 0.36pJ/bit,17 Gbps OOK Receiver ... - 2017 Jul 18
... Programming Language: C Language, Assembly Language, Verilog, VHDL, PL-SQL Full Custom Chip Design: Cadence Virtuoso and Spectre, Mentor Graphics Pyxis. Publication Submitted Research paper in SOCC IEEE conference “A 0.36pJ/bit,17 Gbps OOK Receiver ... - 2017 Jul 18
Electrical Engineering Manager
Rochester, NY
... Understanding of Cadence Constraint Manager, Cadence Concept HDL. Designed the power supply system for Digital Camera. Designed back plane board with four I/O interfaces includes 304 integrate signals and Flexes circuitry. Verified and analysis ... - 2017 Mar 17
... Understanding of Cadence Constraint Manager, Cadence Concept HDL. Designed the power supply system for Digital Camera. Designed back plane board with four I/O interfaces includes 304 integrate signals and Flexes circuitry. Verified and analysis ... - 2017 Mar 17
Engineer Design
Rochester, NY
... Prior to joining Improv Systems, Mark was the Director of Engineering for the Digital IC Design Group of Cadence Design Systems, where in less than 4 years he built a group of over 200 engineers performing over $65M of contract IC design for various ... - 2013 Jan 01
... Prior to joining Improv Systems, Mark was the Director of Engineering for the Digital IC Design Group of Cadence Design Systems, where in less than 4 years he built a group of over 200 engineers performing over $65M of contract IC design for various ... - 2013 Jan 01
Electrical Design
Rochester, NY
... Designed (layout and schematic) and simulated a low -powered, pipelined 8-bit Brent-Kung adder in Cadence; performed simulations to determine the peak power consumption, set and hold times, and functionality with transient analysis. Designed the ... - 2012 Dec 12
... Designed (layout and schematic) and simulated a low -powered, pipelined 8-bit Brent-Kung adder in Cadence; performed simulations to determine the peak power consumption, set and hold times, and functionality with transient analysis. Designed the ... - 2012 Dec 12
Sales Manager
Rochester, NY
... Rochester, NYBusiness Development Mgr / Inside Sales Mgr8/2003 - 8/20052004/2005 Fastest Growing Company in Rochester, NY"Company expansion, North America Solutions Provider for Cadence and OrCAD PCB/IC design software. Total department set-up, ... - 2012 Nov 17
... Rochester, NYBusiness Development Mgr / Inside Sales Mgr8/2003 - 8/20052004/2005 Fastest Growing Company in Rochester, NY"Company expansion, North America Solutions Provider for Cadence and OrCAD PCB/IC design software. Total department set-up, ... - 2012 Nov 17