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Knowledge of circuit design principles and high speed timing and SI

Rochester, New York, United States
April 10, 2018

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Felipe Leite

** ******** ****

Pittsford, NY


IC engineer with over 18 years experience taking designs through the entire flow: design, verification, silicon validation and production test. Experience also includes design-for-testing (DFT) methodologies for system-on-chip

(SoC) and running backend tools for synthesis, scan insertion, formal verification and static timing analysis. Synaptics


New York


Fingerprint Touch Sensor

Product: IC responsible for sensing fingerprint using capacitive and optical technology for the smartphone and PC market.


● Responsible for the design, implementation and verification of different parts of the digital block. Helped develop the testbench infrastructure to drive and check the chip interfaces for verification. Wrote and implemented verification plans.

● Experience with running lint checker on verilog code and fixing errors.

● Led the design-for-testing (DFT) effort. Worked with design and test teams to determine required on-chip test structures needed to achieve our validation and manufacturing testing goals. Implemented custom test logic to meet the DFT requirements.

● Also involved in the backend. Inserted scan (DC-DFTMax), created scan SDC constraints for all test modes, generated scan patterns (Tetramax), and simulated the ATPG patterns against the gate netlist. Coverage goal of 98% for stuck-at and 85% for transition delay was achieved.

● Responsible for memory BIST on all 32 RAM. Performed tradeoff analysis to determine ideal number of MBIST controllers so memories could be tested in parallel to reduce test time while keeping within area and power constraints. Implemented MBIST using Mentor Graphics Tessent tool.

● Worked closely with test team during bring-up and characterization. Supported them by creating and helping debug test vectors.

● Created the necessary design and product documentation. Touch and Display Driver (TDDI)

Product: IC that integrated in-cell capacitive touch with LCD hi-def display driver capabilities. Responsibilities:

● Designed, developed, and tested a block to manipulate pixel data to improve contrast and sharpness as the image moved through the pixel path on the display driver.

● Helped code and verify the I2C interface.

● Wrote C code tests used to verify our microcontroller on-chip debug interface.

● Inserted scan (DC), generated scan patterns (Tetramax), and ran gatesims with all 5 corner SDFs. Scan test time reduction of 10x by adopting Synopsys DFT MAX scan compression automation solution. Generated IDDQ patterns to be implemented to improve coverage.

● Helped create static timing analysis (STA) timing constraints and run Primetime to close time near tapeout. Also implemented ECO in Primetime and generated new SDFs for gate simulations.

● Developed internal tool flows to automate manufacturing test vector generation. The new flow helped us get test vectors created and debugged so we could achieve sample parts screened only 3 days after wafer came out of fab.

Other A ctivities

● Made recruiting trips to colleges to meet with potential candidates, conducted follow up interviews, and made hiring recommendations.

● Served on Social Events Committee and Wellness Committee. Helped plan and coordinate holiday party, summer picnic as well as fitness challenges to promote healthy lifestyles. ATMEL




Automotive Sensor Interface

● Developed a mixed-signal simulation flow to be used for top level verification of an automotive chip that was heavily based on analog cells. Attained an excellent understanding of the Cadence Virtuoso & AMS Designer environments. Coded the testbench and behavioral models using verilog-ams. Insulin Pump

● Served as project manager and technical lead for a custom chip that interfaces with a glucose measuring sensor, and delivers a dose of insulin based on the glucose concentration read.

● Oversaw a small design team responsible for the implementing the digital portion of the chip, integrating the customer designed analog blocks and verifying from top level. Scope changes, due to FDA feedback, and other projects competing for resources were some of the challenges that had to be managed during the design cycle of the project.


● Co-lead the development of an ARM7 SoC (CAP7 that incorporated a metal programmable cell fabric technology to be used as the platform for a new line of structured ASIC solutions.

● Worked with marketing, analog engineers, customers, and the ASIC development team to identify the required product features, and map the system specifications into the chip architecture. Responsible for managing project tasks such as integrating different hardware IP’s and system-level testing.

● Created and helped implement the verification test plan for the SoC. The document covered the necessary steps for RTL code verification and validation of prototype fabrication at the tester. Supported the test engineers during the analog component characterization phase and collaborated with the board designer, firmware developer, and test team to successfully bring up the prototype in the lab. Zigbee Wireless Network Controller

● Served as one of two technical lead engineers in charge of implementing Atmel’s Z-Link Controller chip. This standard product solution integrates encryption hardware with an 8-bit AVR RISC processor and memory structures that are optimized specifically to implement the ZigBee standard. Main design objectives were lowest possible cost with longest possible battery life. Worked closely with firmware developers to identify software functions that could be implemented in hardware to improve overall performance. ASIC Design Engineer

● Took customer design through the ASIC development flow which included integration of test logic(scan and JTAG), creation of timing constraints, synthesis for area/ timing, design verification using third-party and in-house design tools, gate level simulation, physical design (place & route and clock tree insertion), test vector generation/verification, and static timing analysis to verify timing constraints were met. Successfully carried out ASIC development of 8+ designs of varying complexity for different technologies. Motorola




Software Engineer Internship

● Ported a WAP browser, produced by Motorola India Electronics Ltd. (MIEL), to be used within their GSM 2-way pager running on the OS9 operating system.

● Developed and performed test cases on the same device for stability and functionality verification.

● Used C and C++ programming languages to accomplish these tasks. Education

● M.E., Systems Engineering, U niversity of Maryland, College Park, MD (2005–2007)

● B.S., Computer Engineering, R ochester Institute of Technology, Rochester, NY (1998-2002) Skills

EDA Tools: Cadence - Virtuoso, AMSDesigner, Incisive and LEC Synopsys - DesignCompiler, Primetime and TetraMax

MentorGraphics - Tessent

Programming: Verilog, SystemVerilog, C, C++, Perl, Java References available upon request

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