Electrical engineering, embedded software engineer

Siddhant Cocasse

**, ********** ***, ***-* +1-585-***-****

Rochester, NY 14623 ***************@*****.***

A device physics engineer with knowledge of analog circuit designing, Verilog programming, Real-time Embedded systems and working in a clean room. Successful in leading projects independently and working in cross-functional teams. Education

Rochester Institute of Technology,

Rochester, NY Masters (Electrical Engineering) August 2015 - May 2017 S.R.M University, India

Bachelor of Technology (Electrical and

Electronics) September 2011 - May 2015

Coursework: Analog Electronics, Semiconductor Process Integration, Micro-Fabrication, Advanced Field Effect Devices, Advanced Carrier Injection Devices, MEM's Evaluation, Real Time Embedded Systems. Skills

Cadence (Analog and Digital design), Silvaco Tools (Deck-build, ATLAS, Athena), Verilog, Embedded C (QNX-Momentix and Freescale), PLC, SCADA, MATLAB, MATLAB Simulink, SPICE, experienced with working in Clean Room, basic knowledge of Perl and Python.

Academic Projects

High Voltage Swing Two Stage OTA

Designed a two-stage operational amplifier (Op-Amp) with very high voltage swing and low power consumption for given set of operating parameters using Cadence Virtuoso and created a layout for the same using Placement and Routing tool on 45-nm process library. Created test benches to study the operating properties of the circuit. Bandgap Reference Voltage (Brokaw Cell)

Designed a Bandgap reference voltage with output voltage equal to bandgap of silicon. Created a test bench to study the change in output for several types of resistors available on the Cadence 45nm process library to find the one with lowest temperature coefficient.

Designed generic standard cell library in 45nm process design kit using the Cadence Virtuoso design environment Used bottom up design methodology and enhancement of the standard cell library to design cells including inverter, NAND, NOR, XOR, MUX, Full Adder, Flip Flop, Boundary Scan Cell, Boundary Scan Register. Memory access bus arbiter in the DTMF receiver RTL database Used top-down methodology to create a system level design of a memory access bus arbiter module using Verilog HDL and wrote an assembly language test program to verify the operation. Multi-Gate Metal Oxide Field Effect Devices

Wrote a report studying features of multiple-gate FET’s as well as the need to switch from single gate to multiple gate devices, showing how performance of FET’s improves with use of multiple gate devices as the size of devices is reduced to >25 nanometres gate length and focuses on the improvement in threshold voltage of device with the use of double gate FET as compared to single gate FET and carried out necessary simulations using SILVACO: ATHENA and ATLAS tools. Group III Nitride LED’s.

Wrote a report summarizing the different fabrication techniques and how they improve the electroluminescence and power output of small wavelength LED’s using group three nitrides like GaN, AlN, InGaN. Banking environment workflow automation

Developed a QNX Neutrino application simulating a banking environment using ring buffer and implemented single queue with queuing to multi-threaded server.

Servo Motors Automation

Developed an application that controlled a pair of servo motors using the “QNX Purple Box” and Freescale 68HCS12 board. Implemented a 68HCS12 executable, exhibiting multitasking characteristics using communication between the two processors. Certifications

Industrial Training Kota Super Thermal Power Station December 2012 Kota, India

I worked under the team of engineers dealing with monitoring of power generation in the plant through the control room. Also, learned about the power generation and transmission procedure in a thermal power plant, including the chemical and mechanical aspects of generation process.

PLC and SCADA Programming

June 2013 New Delhi, India

Worked on PLC ladder diagram designing on a Schneider PLC and SCADA environment programming using Rs-view.

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