Design Electrical Engineering
Resume:
VYOMA SHARMA
www.linkedin.com/in/vyoma-sharma-b154b851
******@***.***
SUMMARY
* ***** ********** **** *** Design and verification (Verilog)
* **** ********** **** **** and Python
1 Year experience with System Verilog
6 Months experience with CMOS processes
1 Year experience with Full design flow for ASIC/SOC design
1 Year of experience with Cadence EDA /Synopsys tools
EDUCATION
M.S. Electrical Engineering Aug’15 – May’17
Rochester Institute of Technology (RIT), Rochester, NY GPA: 3.3/4.0
Relevant Coursework: Design of Digital Systems, Advanced topics in Design of Digital Systems,
Digital System Verification: Concepts and Technologies, Microelectronic Fabrication,
Real Time Embedded Systems, Analog Electronics, Data Structures & Algorithms
B.E. Electronics & Telecommunication Engineering Aug’08 – Jun’12
Amity University, Noida, India
WORK EXPERIENCE
RIT, Semiconductor and Microsystems Fabrication Lab, Lab Assistant Aug’15 – Mar’17
Calibration and fault analysis of semiconductor fabrication equipment, like AMRAY 1830 SEM, Rudolph Ellipsometer, Tencor Profilometer, ResMap & Spectramap SM300.
Maintained detailed logs of Processes and Measurements carried out in the cleanroom.
Responsible for training of new incoming lab assistant in the operating procedure and protocols utilized in the Laboratory
Wipro Technologies Pvt. Ltd., Software Engineer, Hyderabad, India Jun’12 – Mar’15
Led a team of 3 members and worked as an Software Database Developer, handling Client Licensing Database.
Worked with external and internal partners for handling requirements.
Managed and handled real-time production environment, weekly releases, and production database.
Designed, developed, debugged, documented, refined, and maintained web applications in a time-critical
environment.
SKILL SET
Tools/Equipment: Synopsys Design Compiler, PrimeTime, VCS, Cadence Design Framework II including
Composer, Virtuoso, Spectre, Matlab, Athena Suprem, Atlas, Linux, Microsoft office,
GIT hub, Oscilloscope
Languages: Verilog HDL, System Verilog, UVM, PERL, Python, C, C++, VHDL, Linux, Shell scripting
ACADEMIC PROJECTS
Design and Verification of the operation of 16-bit Fixed-Point Arithmetic Square Root Calculator
Implemented standard low-level block to determine a single bit square root of a number and achieved pipelined implementation by including buffers between recurring instances of the implemented block.
Implemented a system Verilog test-bench in UVM Test Method architecture, with unconstrained random test vectors and input coverage which monitors if thorough testing is performed on the input pins by the random vectors, generated in stimulus.
Synchronization problem between the pipelined DUT and the non-pipelined model is solved by adding a queue / buffer to delay the model output and match it to the corresponding output from the DUT for the same input.
Design of System Verilog test bench for verification of Results Character Conversion(RCC) module
Implemented test bench consisting of stimulus, driver, model, monitor, checker and scoreboard classes, to verify operation of Results Character Conversion block, which identifies the key pressed based on tones detected inside a DTMF Receiver.
Constrained random stimulus, with values limited to the plausible range of the input signals, denoting the power of each tone component, was utilized to generate input test vectors.
Functional coverage and assertions determined the duration and correctness of the tests and confidence in the system.
Design and Verification of Multi-Channel ADPCM codec on Amber SoC (System on Chip) platform
The G.726 ADPCM standard was implemented in Verilog RTL. System was constructed as an SoC with an Amber processor, executing the firmware describing the system and a dedicated Co-Processor performing floating point arithmetic operations utilized in the algorithm.
The implemented hardware components included the Co-Processor, Wishbone Data Bus, Channel Configuration Management, Serial to Parallel I/O interface systems, which was integrated with the open source Amber A25 open source processor implementation.
The implemented system was verified using directed input test vectors coded in Verilog and output vectors generated by bit exact reference model of the ADPCM algorithm for the same inputs. Sign-off included Static Timing closure, and test coverage metrics for the specified standard test vectors.
Design and Verification of a Finite State Machine to arbitrate Bus Access
Implemented a state machine that regulates bus write access between two components of the DTMF Receiver in Verilog and implemented a test bench with directed test cases to verify the system operation. The module was implemented, tested, and synthesized in 180nm Gate Size Technology.
Static Timing analysis was executed for the design to ensure the system achieves timing closure at 50 MHz.
Design and layout of two-stage CMOS Operational Transconductance Amplifier
Designed, Implemented and layout of a 2-Stage Operational Trans-Conductance Amplifier. Performed Design Rule Check (DRC) and Layout Versus Schematic (LVC) check of the implementation in the 45nm Gate Size Technology Library.
Back-end design and implementation of a 45nm CMOS standard cell library
Designed and implemented combinatorial and sequential circuits. Circuit extraction and optimization for power, area and performance. Worked on physical layout (place-route) of the hierarchical cells (16-bit carry select adder with boundary scan structure). Performed circuit simulation reliability verification/validation using design Rule (DRC)& Layout vs Schematic checks(LVS).
Design and implementation of an embedded, real-time stand-alone system to provide a rough indication of voltage
Involved parallel communication between Freescale board (driving servos) and QNX neutrino (ADC). Indicated voltage using Servo motors.
Perl & Python Scripting Project
Automated test execution and data logging for Verilog module test benches and implemented an assembler to interpret assembly code.
Implemented a script to generate variable resolution fixed point calculator based on input size, output resolution and type of I/O data.
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