| Resume alert | Resumes 61 - 70 of 114 |
Professional Experience Design Engineer
Hyderabad, Telangana, India
... EDA Tools : Modelsim, Xilinx ISE Design Suite, Questasim, Cadence Domain : ASIC/FPGA Design Flow, Digital Design concepts Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage Verification Methodologies : Coverage Driven Verification. ... - 2016 Mar 25
... EDA Tools : Modelsim, Xilinx ISE Design Suite, Questasim, Cadence Domain : ASIC/FPGA Design Flow, Digital Design concepts Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage Verification Methodologies : Coverage Driven Verification. ... - 2016 Mar 25
Design Engineering
Hyderabad, Telangana, India
... Completed CVCP certification from Cadence and looking for opportunity in semiconductor industry. Currently working in the IT sector at ‘NTT DATA GDS’ for ‘SUPREVALU’ project in Finance domain. Currently working with the technology UNIX and COBOL. ... - 2016 Jan 17
... Completed CVCP certification from Cadence and looking for opportunity in semiconductor industry. Currently working in the IT sector at ‘NTT DATA GDS’ for ‘SUPREVALU’ project in Finance domain. Currently working with the technology UNIX and COBOL. ... - 2016 Jan 17
Project Design Engineer
Hyderabad, Telangana, India
... Hands on experience on Cadence Virtuoso, Caliber DRV, SOC encounter ( cadence ) tools . Hands on experience on DRC, ERC, LVS cleaning using the Calibre DRV tool Hands on experience on Custom layout development and Verification. Technical Skills : ... - 2016 Jan 06
... Hands on experience on Cadence Virtuoso, Caliber DRV, SOC encounter ( cadence ) tools . Hands on experience on DRC, ERC, LVS cleaning using the Calibre DRV tool Hands on experience on Custom layout development and Verification. Technical Skills : ... - 2016 Jan 06
Project Engineer
Hyderabad, Telangana, India
... Software Proficiency: Can work in different Tools & Editors such as XILINX 9.21 KEIL UVISION 4 CADENCE SENTAURUS TCAD TURBO C/C++ JDK Technical Knowledge: Languages: Basics of C/C++ Embedded C CORE JAVA VHDL Verilog Operating Systems : Can work in ... - 2015 Dec 28
... Software Proficiency: Can work in different Tools & Editors such as XILINX 9.21 KEIL UVISION 4 CADENCE SENTAURUS TCAD TURBO C/C++ JDK Technical Knowledge: Languages: Basics of C/C++ Embedded C CORE JAVA VHDL Verilog Operating Systems : Can work in ... - 2015 Dec 28
VLSI Design Engineer
Hyderabad, Telangana, India
... DESIGN ENGINEER SKILL SET: HDL : Verilog, VHDL Verification : System Verilog, OVM, UVM(Learning) Scripting : Perl, Python(Learning) Other Languages : C,C++(Beginner) Simulators : ModelSim, ISim, QuestaSim Synthesizers : Xilinx, Altera, Cadence. ... - 2015 Dec 23
... DESIGN ENGINEER SKILL SET: HDL : Verilog, VHDL Verification : System Verilog, OVM, UVM(Learning) Scripting : Perl, Python(Learning) Other Languages : C,C++(Beginner) Simulators : ModelSim, ISim, QuestaSim Synthesizers : Xilinx, Altera, Cadence. ... - 2015 Dec 23
Project Design
Hyderabad, Telangana, 500034, India
... Andrews High School APRIL - 2002 85.83 % PROFESSIONAL SKILLS Cadence Tools : VIRTUOSO 1.6.1.4 VHDL & VERILOG - Can write reliable and efficient code for simulation and synthesis, mainly for Xilinx FPGAs. Awareness of device targeting in source code ... - 2015 Nov 16
... Andrews High School APRIL - 2002 85.83 % PROFESSIONAL SKILLS Cadence Tools : VIRTUOSO 1.6.1.4 VHDL & VERILOG - Can write reliable and efficient code for simulation and synthesis, mainly for Xilinx FPGAs. Awareness of device targeting in source code ... - 2015 Nov 16
Project Engineering
Hyderabad, Telangana, India
... Tools: MATLAB, Multisim, Cadence - NC, Spectre, Virtuoso ADE, Assura, Encounter RTL Compiler, SOC Encounter CERTIFICATIONS 1. Certified in Physical design through Cadence VLSI Certification Program (CVCP) PROJECTS 1. Advance Peripheral Bus (APB) ... - 2015 Oct 07
... Tools: MATLAB, Multisim, Cadence - NC, Spectre, Virtuoso ADE, Assura, Encounter RTL Compiler, SOC Encounter CERTIFICATIONS 1. Certified in Physical design through Cadence VLSI Certification Program (CVCP) PROJECTS 1. Advance Peripheral Bus (APB) ... - 2015 Oct 07
Power Data
Himayathsagar, Telangana, 501504, India
... 2007 87.66 TECHNICAL SKILLS: Basics of C, Verilog HDL, Xilinx, Modelsim, Cadence NC Launch, Cadence RC, Cadence Encounter, Basics of TCL, Basics of PERL, Basics of MAT Lab PROJECTS: Topic An Efficient Hardware Realization of Distributed Arithmetic ... - 2015 Jul 02
... 2007 87.66 TECHNICAL SKILLS: Basics of C, Verilog HDL, Xilinx, Modelsim, Cadence NC Launch, Cadence RC, Cadence Encounter, Basics of TCL, Basics of PERL, Basics of MAT Lab PROJECTS: Topic An Efficient Hardware Realization of Distributed Arithmetic ... - 2015 Jul 02
Project Design
Himayathsagar, Telangana, 501504, India
... School SKILL SET: Languages :C Scripting Languages : Perl,tcl basics Operating System : Windows, Linux HDL Languages : Verilog VLSI CAD Tools Cadence Tool Suite (Virtuoso, Encounter, NC Launch,TINA-TI) PERSONAL TRAITS: 1. Reliable and hard working ... - 2015 Jun 16
... School SKILL SET: Languages :C Scripting Languages : Perl,tcl basics Operating System : Windows, Linux HDL Languages : Verilog VLSI CAD Tools Cadence Tool Suite (Virtuoso, Encounter, NC Launch,TINA-TI) PERSONAL TRAITS: 1. Reliable and hard working ... - 2015 Jun 16
Strong in Digital Electronics,Good Knowledge in Verilog and VHDL
Hyderabad, Telangana, India
... : VHDL, Verilog EDA Tools : Xilinx ISE, Cadence Others : Keil, Proteus PROJECTS FPGA Implementation Of High Efficiency Carry-Select Adder January 2015- May 2015 Need to analyse the logic operations involved in the Conventional and BEC-based CSLAs. ... - 2015 Jun 03
... : VHDL, Verilog EDA Tools : Xilinx ISE, Cadence Others : Keil, Proteus PROJECTS FPGA Implementation Of High Efficiency Carry-Select Adder January 2015- May 2015 Need to analyse the logic operations involved in the Conventional and BEC-based CSLAs. ... - 2015 Jun 03