Power Data
Resume:
MAKKA SATYA RAJEEV
Mail Id : ***********.*@*****.***
OBJECTIVE:
To work in a challenging environment where I can implement my technical knowledge blended with innovating thinking for optimal usuage of my skills which will help me to realize my potienal and contribute to the growth of organization.
ACADEMIC QUALIFICATION:
LEVEL OF
EDUCATION
INSTITUTION
BOARD/UNIVERSITY
YEAR OF
PASSING
AGGREGATE
(in %)
M.Tech
(VLSI)
VIT University VIT University 2015 8.77
(CGPA)
B.Tech
(ECE)
GMRIT Jawaharlal Nehru
Technological
University, Kakinada
2013
80.00
Intermediate
Sri Chaitanya junior
college
Board of Intermediate
Education, A.P.
2009
94.40
S.S.C
Venus Public School Board of Secondary
Education, A.P.
2007
87.66
TECHNICAL SKILLS:
Basics of C, Verilog HDL, Xilinx, Modelsim, Cadence NC Launch, Cadence RC, Cadence Encounter, Basics of TCL, Basics of PERL, Basics of MAT Lab PROJECTS:
Topic An Efficient Hardware Realization of Distributed Arithmetic based Discrete Cosine Transform
Language Verilog HDL
Tools Modelsim, Cadence RC, Cadence Encounter
Description
DCT technique is used in image and video compression. If image and video size increases area occupied by the memory and power consumed by the multipliers are more. To reduce the power and area, an efficient design for the implementation of DCT using cyclic convolution and Grouped Distributed Arithmetic technique is proposed. In Grouped Distributed Arithmetic, Read Only Memory size could be reduced compared to convolutional DA based on the cyclic convolution. To implement the transform length N=13 of 1-D DCT, proposed method requires 31 Look Up Tables (LUT) while conventional DA requires 384 Look Up Tables. Therefore power and area are reduced. Topic Low Power FFT Processor with Reduced Addressing Logic Language Verilog HDL
Tools Modelsim, Cadence RC, Cadence Encounter
Description
FFT processor is a most useful processor now a days but the power consumption and hardware complexity is more. In order to reduce the power consumption and hardware complexity,memory is divided into multiple memory banks by reducing the addresses and by reducing the accessing time of twiddle factors .“In-Place” method is used to reduce the memory usage by storing the new butterfly operation results in the same memory and reusing that memory for next butterfly operations. Topic Verilog Implementation of a Data Hiding Using Image Interpolation Language Verilog HDL
Tools Modelsim, Xilinx, Cadence RC, Cadence Encounter Description
Data security is an important factor now a day. There are different techniques to secure data. Interpolation is widely used in imaging world to hide data by using technique called Neighbor mean Interpolation. In this technique secrete data is added to average of the neighbor pixels and place between those neighboring pixels. Topic Design of Discrete Frequency Coded Radar Sequence using Particle Swarm Optimization
Language MAT Lab
TOOL MAT Lab
Description
Pulse compression is used to resolve the closely spaced targets. In Order to improve detection performance and to avoid the masking of small targets, the Switching order of the phase or frequency is the point of interest in the design of such Sequences. PSO algorithm is used effectively for the design of DFC waveforms that have desired correlation properties. The sequence length varies from 100 to 1000 and its resultant synthesized sequences are better than the binary and poly phase. CO-CURRICULAR ACTIVITIES:
Presented Paper on “IRIS Technology”.
Presented paper on “Introduction of Electronics into Automobiles”.
Presented poster on “Artificial Heart” in JNTU Vizianagaram EXTRA CURRICULAR ACTIVITES:
Member of ISTE, IE and IETE student’s chapter, ECE Department. ACHIEVEMENTS AND AWARDS:
Awarded FIRST prize “Technical Quiz” Twice in ISTE chapter organized by department level.
Awarded FIRST Prize in poster presentation in JNTU Vizianagaram.
Awarded SECOND Prize in paper presentation in ISTE student’s chapter in department level.
Received token of appreciation for being branch topper. HOBBIES:
Playing Cricket
Listening to Music
PERSONEL DETAILS:
Date of birth : 13-07-1992
Father’s Name : Appala Naidu
Mother’s Name : Sarala
Languages Known : English and Telugu
DECLARATION:
I hereby certify that all the information provided above is true to the best of my Knowledge. Place:
Date: M.SATYA RAJEEV.
Contact this candidate