Resume

Sign in

VLSI Design Engineer

Location:
Hyderabad, Telangana, India
Posted:
December 23, 2015

Contact this candidate

Resume:

CURRICULUM VITAE

Panda Vinay Kumar

Email ID : acswd7@r.postjobfree.com

Contact no : 089******** / 073********

CARRER OBJECTIVE

Looking for a responsible position as a VLSI design engineer with a view to utilize and enhance my skills and experience towards professional growth.

EXPERIENCE

Organization: Krest Technology, Hyderabad

Duration: July 2015 till date

Designation: DESIGN ENGINEER

SKILL SET:

HDL : Verilog, VHDL

Verification : System Verilog, OVM, UVM(Learning)

Scripting : Perl, Python(Learning)

Other Languages : C,C++(Beginner)

Simulators : ModelSim, ISim, QuestaSim

Synthesizers : Xilinx, Altera, Cadence.

ACADEMIC PROFILE

School/College

DEGREE

Branch/Group

BOARD

Year of passing

Aggregate

Centre for Development of Advanced Computing

Post Graduation-Diploma

Integrated VLSI and Embedded System Design

Department of Electronics and Information Technology

2015

68.3%

Aurora’s Technological and Research Institute

B.Tech

ELECTRONICS AND COMMUNICATIONS

JNTUH

2014

62.94%

Narayana Junior College

Intermediate

MPC

State Board of Intermediate

2010

75.50%

Bhashyam Public School

10th standard

SSC

State Secondary Board

2008

79.50%

PROJECT

Recursive Approach to the Design of a Parallel Self-Timed Adder

Platform: RTL Coding (Verilog) Duration: 3 Days

Tools: Xilinx, Isim

Description: Here an asynchronous parallel self-timed adder (PASTA) using the algorithm originally proposed. The design of PASTA is regular and uses half-adders (HAs) along with multiplexers requiring minimal interconnections. Thus, it is suitable for VLSI implementation. The design works in a parallel manner for independent carry chain blocks. The implementation in this brief is unique as it employs feedback through XOR logic gates to constitute a single-rail cyclic asynchronous sequential. The proposed circuit manages automatic single-rail pipelining of the carry inputs separated by propagation and inertial

delays of the gates in the circuit path.

Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications

Platform: RTL Coding (Verilog) Duration: 3 Days

Tools: Xilinx, Isim

Description: The dedicated short-range communication (DSRC) is an emerging technique to push the intelligent transportation system into our daily life. The DSRC standards generally adopt FM0 and Manchester codes to reach dc-balance, enhancing the signal reliability. Nevertheless, the coding-diversity between

the FM0 and Manchester codes seriously limits the potential to design a fully reused VLSI architecture for both. Here, the similarity-oriented logic simplification (SOLS) technique is proposed to overcome this limitation. The SOLS technique improves the hardware utilization rate from 57.14% to 100% for both FM0 and Manchester encodings.

32 Bit 32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler

Platform: RTL Coding (Verilog) Duration: 1 Week

Tools: Xilinx, Modelsim

Description: Here multiprecision (MP) reconfigurable multiplier is presented that incorporates variable precision, parallel processing (PP), razor-based dynamic voltage scaling (DVS), and dedicated MP operands scheduling to provide optimum performance for a variety of operating conditions. All of the building blocks of the proposed reconfigurable multiplier can either work as independent smaller-precision multipliers or work in parallel to perform higher-precision multiplications. A dynamic voltage scaling management unit configures the multiplier to operate at the proper precision. Finally, the proposed novel MP multiplier can further benefit from an operands scheduler that rearranges the input data, hence to determine the optimum voltage operating conditions for minimum power consumption.

Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip

Platform: RTL Coding (Verilog) Duration: 3 Days

Tools: Xilinx, Isim

Description: Here a set of data encoding schemes aimed at reducing the power dissipated by the links of an NoC. The proposed schemes are general and transparent with respect to the underlying NoC fabric. The focus on techniques aimed at reducing the power dissipated by the network links. In fact, the power

dissipated by the network links is as relevant as that dissipated by routers and network interfaces (NIs) and their contribution is expected to increase as technology scales.

General Purpose Test Simulator and Format Analyzer

Platform: RTL Coding (Verilog) Duration: 1 Month

Tools: Modelsim, Precision Synthesis

Description: The scope of the project is to develop a UART in Verilog which can receive the satellite data through front end hardware. The received data should be analyzed and checked for the detection of frame sync. From the available frame sync formats, data has to be checked if one among the formats appears in the data. The frame syncs should be detected and bit errors in the frame sync code are to be detected and logged.

General Purpose Convolutional encoder and Viterbi Decoder for Satellite Communication (ISRO)

Platform: RTL Coding (VHDL) Duration: 3 Months

Tools: Altera Quartus II, Modelsim

Description: The basic convolution encoder and Viterbi decoder in the standard format has been be implemented in the VHDL code and result has been be checked using the simulator. Once the simulation results are successful the MAX 7000 EPLD will be used and wired on breadboard.

EXTRACURRICULAR ACTIVITIES

Coordinator of The 1st World Parliament of Spirituality 17th-21st Dec 2012

Chief Coordinator for The Technical Talk on PSOC on October 29 and 20,2012

Volunteer of SCIENTIA 2K11 at ATRI on 11th & 12thNov’ 2011.

Captain of NATIONAL GREEN CORPS during the year 2005-2006.

Participated in the International Student Conference on VLSI Deign and Embedded Systems at Hyderabad on 9th & 10th Jan’2012.

PERSONAL DETAILS

Date of Birth

:

7th January, 1993

Gender

:

Male

Languages Known

:

Telugu, Hindi & English.

DECLARATION

I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above mentioned particulars.

Hyderabad

Date: 22-12-2015 (PANDA VINAY KUMAR)



Contact this candidate