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SystemVerilog UVM Verification Engineer resume in Denton, TX, 76208 - November 2026
Harika P
+1-972-***-**** ******.*@***********.*** Open to Relocate
SUMMARY
Design & Verification Engineer with 5+ years of experience in SystemVerilog, UVM, SVA, constrained-random testing, and coverage-driven verification. Specialized in CPU, SoC, memory, low-power, and automotive IP...
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