SystemVerilog UVM Verification Engineer

Harika P

+1-972-***-**** ******.*@***********.*** Open to Relocate

SUMMARY

Design & Verification Engineer with 5+ years of experience in SystemVerilog, UVM, SVA, constrained-random testing, and coverage-driven verification. Specialized in CPU, SoC, memory, low-power, and automotive IP verification using AMBA protocols, CDC/RDC analysis, formal verification, and emulation. Experienced in developing reusable verification environments, debugging RTL with VCS and Verdi, automating regressions, and driving coverage closure through targeted test development and systematic failure analysis. SKILLS

RTL Design: SystemVerilog, Verilog, Synthesizable RTL, Microarchitecture, FSMs, Datapaths, Control Logic, Clock & Reset Design Verification Methodologies: UVM, SystemVerilog Assertions (SVA), Constrained-Random Testing, Coverage-Driven Verification, Functional Coverage, Code Coverage, Coverage Closure, Formal Property Checking, Scoreboards, Verification Planning CPU & SoC Verification: RISC-V Verification, Memory Subsystems, Interconnect Verification, Protocol Compliance, Interrupt Verification, Reset Verification, Power-State Verification, Cache Verification, Error Injection Protocols: AMBA, AXI, AXI4-Lite, APB, PCIe, USB, Ethernet, CAN, LIN EDA & Analysis: Synopsys VCS, Verdi, Specman e, CDC/RDC Analysis, JasperGold Formal Verification, Palladium Emulation Automation & Engineering: Perl, Tcl, Shell Scripting, Linux, Make, Regression Automation, Log Analysis, Seed Management, Failure Classification, Git, Requirements Traceability

EXPERIENCE

Design & Verification Engineer Qualcomm, USA May 2025 – Present

Engineered reusable SystemVerilog/UVM environments for Qualcomm CPU-subsystem and power-management IP, integrating agents, monitors, scoreboards, and coverage models to validate interface transactions, control sequencing, and corner-case behavior.

Authored constrained-random and directed tests for AXI/APB transactions, reset sequencing, interrupt handling, and power-state transitions, validating protocol behavior, access restrictions, boundary conditions, and illegal state changes.

Embedded SVA protocol and power-state checkers for handshake ordering, reset behavior, and illegal transitions, detecting 30+ RTL issues before subsystem integration and enabling earlier correction of control defects.

Orchestrated VCS regressions through seed management, log parsing, failure classification, and rerun control across 2,000+ test executions, standardizing failure triage and isolating recurring issues from new regressions.

Diagnosed RTL and testbench failures using Verdi waveform analysis, transaction tracing, and signal-level correlation, isolating protocol violations, reset-sequencing defects, and clock-domain interactions for targeted RTL fixes.

Assessed CDC/RDC paths across CPU and subsystem interfaces using structural checks, synchronizer analysis, and targeted simulation, closing 25+ clock- and reset-domain violations before integration.

Closed functional, code, assertion, and cross-coverage gaps by refining stimulus and adding corner-case tests for power transitions, back-to-back traffic, and reset recovery, achieving 95%+ functional coverage. Design & Verification Engineer Accenture, INDIA Aug 2019 – Jul 2023

Verified automotive SoC IPs for ADAS and infotainment using Specman e and coverage-driven verification, developing reusable components for memory controllers, DMA, interrupt, and peripheral interfaces to uncover functional and integration defects.

Constructed transaction-level and scenario-based tests for PCIe, USB, Ethernet, CAN, and LIN, validating packet handling, data integrity, interrupt behavior, error recovery, and low-power operation across automotive SoC interfaces.

Formalized JasperGold properties and bounded proofs for arbitration logic, FIFO control, access permissions, and safety-critical paths, identifying 25+ corner-case RTL defects before subsystem integration.

Exercised Palladium and FPGA-based emulation to validate subsystem interactions under extended traffic, analyzing hardware traces and stress-test results to identify integration and long-duration execution issues across 500+ cumulative hours.

Evaluated SRAM, cache, DMA, and shared-memory interfaces through parity/ECC injection, address-alignment checks, and data- consistency analysis, uncovering 30+ functional, integrity, and access-protection issues.

Automated test generation, simulator setup, log parsing, failure classification, and regression reporting using Perl, Tcl, and Make, managing 2,500+ test executions and standardizing regression analysis and failure triage.

Modeled automotive SoC peripheral registers and developed register-access sequences, validating reset values, access permissions, field behavior, and error responses across functional and negative-access scenarios.

Documented verification signoff evidence through requirements traceability, coverage analysis, defect reviews, and safety-verification reporting, closing 90%+ of assigned coverage targets in coordination with RTL and validation teams. PROJECTS

RISC-V Processor Verification Using SystemVerilog and UVM

Built a SystemVerilog/UVM verification environment for a 5-stage RISC-V processor, integrating reusable agents, drivers, monitors, scoreboards, and a reference model for instruction-level and architectural-state checking.

Generated directed and constrained-random tests for arithmetic, branching, load/store operations, pipeline hazards, forwarding, stalls, exceptions, and illegal instruction handling.

Low-Power SoC Interconnect and Memory Subsystem Verification

Developed a reusable SystemVerilog/UVM environment for a low-power SoC subsystem containing AXI, APB, SRAM, clock-control, and power-management interfaces, enabling modular stimulus, transaction checking, and coverage analysis.

Created transaction-level tests for AXI/APB transfers, arbitration, address decoding, response ordering, back-to-back traffic, and error handling to validate data integrity and boundary conditions. EDUCATION

Master of Science in Artificial Intelligence May 2025 The University of North Texas, Denton, Texas

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