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RTL Verification Engineer (UVM/SystemVerilog) resume in Grapevine, TX - September 2026
Rashid Syed
**************@*****.*** • LinkedIn • 940-***-****
PROFESSIONAL SUMMARY
Design Verification Engineer with experience in RTL verification using SystemVerilog and UVM, and internship exposure to Analog and Mixed-Signal (AMS) verification. Proficient in developing UVM-based...
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