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SoC/UVM Design Verification Engineer resume in Bareilly, Uttar Pradesh, India - September 2026
ANKUR PANGHAL
+1-559-***-**** **************@*****.*** linkedin.com/in/ankur09
PROFESSIONAL SUMMARY
Design Verification Engineer with 5+ years of experience in ASIC and SoC verification using SystemVerilog and UVM. Experienced in developing reusable UVM verification environments, constrained...
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