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Senior ASIC/FPGA Design Verification Engineer resume in St. Louis, MO - September 2026
Faizan
Senior Design Verification Engineer **********@*****.*** 314-***-****
PROFESSIONAL SUMMARY
•Senior Design Verification Engineer with 6+ years of experience in ASIC and FPGA verification using System Verilog and UVM methodologies across networking, automotive, medical, and...
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