Senior ASIC/FPGA Design Verification Engineer

Faizan

Senior Design Verification Engineer **********@*****.*** 314-***-****

PROFESSIONAL SUMMARY

•Senior Design Verification Engineer with 6+ years of experience in ASIC and FPGA verification using System Verilog and UVM methodologies across networking, automotive, medical, and high-performance SoC platforms.

•Strong expertise in developing scalable UVM verification environments and reusable testbench components including agents, drivers, monitors, sequencers, and scoreboards for complex digital designs.

•Extensive experience verifying SoC subsystems including CPU interfaces, memory controllers, cache hierarchies, and high-speed protocols such as AMBA AXI, PCIe Gen5/Gen6, Ethernet, I2C, and SPI.

•Hands-on experience validating advanced memory subsystems including DDR5, LPDDR5, and HBM3, ensuring correct timing behavior, transaction integrity, and high-throughput data movement in complex SoC architectures.

•Skilled in developing System Verilog Assertions (SVA), constrained-random test scenarios, and functional coverage models to validate protocol compliance and identify verification gaps before silicon tape-out.

•Proficient in debugging RTL and testbench issues using waveform analysis, protocol checks, and assertion failures with industry-standard tools such as Synopsys VCS, Cadence Xcelium, QuestaSim, and Verdi.

•Experienced in executing constrained-random verification flows and analyzing functional coverage results to improve verification completeness and test quality.

•Hands-on experience with clock domain crossing (CDC) verification and block-level to subsystem-level verification flows for complex multi-core SoC architectures.

•Experienced in regression automation and verification infrastructure development using Python, Perl, and Tcl, improving regression efficiency and simulation productivity.

•Worked closely with RTL designers and architecture teams to reproduce issues, analyze root causes, and validate design fixes during verification cycles.

•Contributed to verification of safety-critical automotive systems compliant with ISO 26262 ASIL-D and medical electronic systems aligned with ISO 13485 and IEC 60601 standards.

•Strong understanding of the complete ASIC development lifecycle including pre-silicon verification, coverage closure, regression analysis, and post-silicon bring-up support.

TECHNICAL SKILLS

Programming Languages

System Verilog, Verilog, Python, Perl, Tcl

Verification Methodologies

UVM, Constrained Random Verification, Coverage Driven Verification, Assertion Based Verification

Protocols

AMBA AXI, AHB, APB, PCIe Gen5/Gen6, Ethernet

Memory Interfaces

DDR5, LPDDR5, HBM3

Verification Techniques

Functional Coverage, Code Coverage, System Verilog Assertions (SVA), Regression Testing

EDA Tools

Synopsys VCS, Cadence Xcelium, QuestaSim, Verdi, Cadence Palladium, Synopsys Zebu (Exposure)

Automation

Python scripting, Perl scripting, Shell scripting, Regression automation, Log analysis

Verification Domains

SoC Verification, Protocol Verification

Design Concepts

SoC Architecture, Cache Coherency

PROFESSIONAL EXPERIENCE

Qualcomm- Senior Design Verification Engineer

July 2025 –present Santa clara, CA

Developed UVM-based System Verilog verification environments for next-generation networking SoCs used in high-performance communication systems.

Designed reusable UVM agents, drivers, monitors, sequencers, and scoreboards to verify complex digital IP blocks and protocol interfaces.

Implemented constrained-random test sequences and functional coverage models to validate corner-case scenarios and ensure verification completeness.

Verified AXI-based Network-on-Chip (NoC) interconnect fabric connecting CPUs, memory controllers, DMA engines, and peripheral subsystems.

Developed and maintained SystemVerilog/UVM testbenches to verify PCIe IP and SoC-level PCIe functionality across different configurations.

Verified PCIe link training and LTSSM states, including Detect, Polling, Configuration, L0, Recovery, and low-power states.

Developed UVM sequences and tests for PCIe Configuration Space, BARs, TLP/DLLP transactions, and enumeration.

Verified PCIe Gen3/Gen4/Gen5 functionality, including link width, speed negotiation, data transfer, and error scenarios.

Developed UVM traffic generators to validate NoC routing, arbitration, ordering rules, and deadlock-free packet movement across multiple initiators and targets.

Executed performance verification by measuring latency, throughput, bandwidth utilization, and congestion behavior under high-traffic scenarios.

Verified CPU subsystem functionality including instruction fetch, decode, execute, and memory access paths within a multicore SoC environment.

Developed UVM sequences to validate integer pipeline behavior, hazard handling, instruction ordering, and exception processing.

Verified Load Store Unit (LSU) functionality including load/store transactions, memory ordering rules, and cache interactions.

Developed assertions and functional coverage models to validate pipeline stalls, forwarding logic, and corner-case execution scenarios.Collaborated with hardware teams to support emulation-based verification workflows using Cadence Palladium and Synopsys Zebu platforms, enabling faster validation of complex SoC scenarios prior to silicon tape-out.

Performed CDC verification to ensure reliable synchronization across multiple clock domains in complex SoC architectures.

Debugged RTL and testbench failures using Verdi waveform analysis, identifying root causes and collaborating with RTL designers to resolve issues.

Automated regression testing using Python and Tcl scripts, improving simulation workflow efficiency and reducing debugging turnaround time.

Achieved functional coverage closure across multiple IP blocks by expanding constrained-random stimulus and coverage models before design sign-off.

Identified and resolved critical RTL bugs during pre-silicon verification, preventing potential silicon design escapes.

Contributed to successful SoC tape-out by driving verification closure and collaborating with architecture and RTL teams.

Environment: System Verilog, UVM, Verilog, AMBA AXI/AHB/APB, PCIe Gen5/Gen6, Ethernet, DDR5, LPDDR5, HBM3, System Verilog Assertions (SVA), Constrained Random Verification, Coverage Driven Verification, CDC Verification, Synopsys VCS, Cadence Xcelium, Questa Sim, Verdi, Python, Tcl, Regression Automation, Linux.

AMD - Design Verification Engineer

Mar 2023 – June 2025 Austin, Texas

Built UVM Instruments-based verification environments from scratch for industrial SoC platforms used in automation and embedded computing systems.

Developed test sequences, stimulus generators, and coverage collectors to validate system functionality across multiple integrated IP blocks.

Verified communication protocols including AMBA AXI, I2C, and SPI, ensuring correct transaction flow and protocol timing behavior.

Debugged CPU subsystem failures involving instruction execution, cache coherency, and memory consistency issues.

Created directed and constrained-random tests for Memory Read/Write, Configuration, Completion, and other PCIe transaction types.

Implemented SystemVerilog assertions and functional coverage to verify protocol requirements and improve coverage closure.

Used PCIe VIP/BFM for protocol-level verification and monitored TLP/DLLP traffic between Root Complex and Endpoint.

Created constrained-random tests targeting pipeline hazards, branch scenarios, and concurrent memory access conditions.

Analyzed transaction latency and bandwidth efficiency across AXI-based subsystem interconnects using performance monitors and protocol checkers.

Validated memory controller functionality and subsystem integration involving DDR memory interfaces.

Supported FPGA prototyping environments for early SoC validation, assisting with design bring-up and debugging functional issues prior to full silicon availability.

Validated low-level debug and communication interfaces including UART and JTAG during subsystem verification and early bring-up testing.

Implemented coverage-driven verification methodologies, creating functional coverage models to track verification progress and corner-case scenarios.

Conducted regression testing and failure analysis, improving verification quality and reducing design escapes prior to tape-out.

Performed extensive RTL debugging using waveform analysis tools, collaborating with design teams to resolve functional failures.

Automated regression workflows and log analysis using Python and Perl scripting, improving simulation efficiency.

Identified multiple design issues during pre-silicon verification that helped improve system stability and reliability.

Environment: System Verilog, UVM, Verilog, AMBA AXI/AHB/APB, I2C, SPI, DDR Memory Interfaces, Functional Coverage, Assertion Based Verification, Constrained Random Verification, Synopsys VCS, QuestaSim, Verdi, Python, Perl, Regression Automation, Linux.

ACL Digitals - Design Verification Engineer

May 2020 - Dec 2022 Hyderabad, India

Developed System Verilog testbenches and UVM verification components to validate FPGA and ASIC digital logic blocks used in automotive and medical electronic systems.

Implemented reusable UVM infrastructure including drivers, monitors, sequencers, and scoreboards to support scalable verification environments.

Performed protocol verification for AMBA AXI/AHB/APB interfaces, ensuring correct transaction ordering and data integrity.

Contributed to verification of automotive control systems compliant with ISO 26262 ASIL-D functional safety standards.

Supported verification activities for medical electronic systems aligned with ISO 13485 and IEC 60601 regulatory requirements.

Developed directed and constrained-random tests to validate control logic and embedded subsystem functionality.

Executed regression suites and tracked verification metrics including functional coverage and code coverage.

Analyzed simulation waveforms to debug functional failures and collaborated with RTL engineers to resolve design issues.

Assisted with verification planning, documentation, and regression infrastructure improvements across multiple FPGA and ASIC projects.

Environment: System Verilog, Verilog, UVM, AMBA AXI/AHB/APB, FPGA Verification, Assertion Based Verification, Functional Coverage, Constrained Random Verification, Synopsys VCS, QuestaSim, Verdi, Python, Perl, Tcl, Regression Testing, Linux.

Education: Bachelors in Electronics & Communication – Osmania University (May 2020)

Contact this candidate