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SystemVerilog UVM Design Verification Engineer resume in San Jose, CA - September 2026
TEJANAND PATTEMMUNIRATHNAMROSE
DESIGN VERIFICATION ENGINEER
San Jose, CA 95112 +1-408-***-**** ************@*****.*** LinkedIn PROFESSIONAL SUMMARY
Design Verification Engineer with hands-on experience building SystemVerilog/UVM-based verification environments for IP and subsystem-level RTL....
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