SystemVerilog UVM Design Verification Engineer

TEJANAND PATTEMMUNIRATHNAMROSE

DESIGN VERIFICATION ENGINEER

San Jose, CA 95112 +1-408-***-**** ************@*****.*** LinkedIn PROFESSIONAL SUMMARY

Design Verification Engineer with hands-on experience building SystemVerilog/UVM-based verification environments for IP and subsystem-level RTL. Experienced in verification planning, reusable testbench development, constrained-random stimulus, SVA, functional and code coverage, regression debugging, and waveform-based root-cause analysis. Verified FIFO, AXI/AHB/APB interconnect, pipelined datapaths, and PCIe transaction-layer behavior using simulation-driven verification. Strong foundation in RTL design, digital logic, memory hierarchy, cache coherence, processor architecture, Python, and C/C++. TECHNICAL SKILLS

Hardware Description Languages: Verilog, SystemVerilog Verification: UVM, SystemVerilog OOP, SVA, constrained-random verification, functional coverage, code coverage, waveform debugging, regression debugging, formal verification fundamentals Protocols: AMBA AXI, AXI-Lite, AHB, APB, PCIe Fundamentals, SPI, I2C, UART RTL & Digital Design: RTL Design, FSM Design, Pipelining, FIFO Design, Static Timing Analysis (STA) Computer Architecture: Memory Hierarchy, Cache Coherence, Cache Architecture, Processor Architecture, MIPS 5-Stage Pipeline Tools: Synopsys VCS, QuestaSim, ModelSim, Xilinx Vivado, GTKWave, Design Compiler Programming: Python, C/C++, Git

EXPERIENCE

San Jose State University Design & Verification - Research Assistant. May 2025 – Present

• Authored SystemVerilog/UVM verification test plans for a Zynq FPGA-based image-processing/video pipeline, covering pipeline stages, reset behavior, corner cases, and end-to-end data-integrity checks.

• Expanded FPGA verification infrastructure with directed and corner-case scenarios across 3 key RTL areas - line buffer, MAC, and control logic - to strengthen validation of streaming datapath behavior.

• Debugged 3 major classes of subsystem integration issues - pipeline hazards, timing mismatches, and data-alignment errors - using RTL simulation, waveform analysis, and root-cause isolation.

• Correlated simulation results with FPGA hardware behavior to validate end-to-end Sobel edge-detection functionality and resolve RTL- to-hardware integration mismatches.

Maven Silicon Design & Verification Trainee Sep 2022 - May 2023

• Built a reusable SystemVerilog/UVM verification environment for FIFO RTL with driver, monitor, scoreboard, constrained-random stimulus, assertions, functional coverage, and Python-based verification support, uncovering corner-case functional issues.

• Verified 6 critical FIFO scenarios - full, empty, overflow, underflow, reset, and simultaneous read/write - using assertions and functional coverage to exercise boundary and error conditions.

• Designed and verified an FSM-based AHB-to-APB bridge in SystemVerilog and synthesized the RTL using Xilinx Vivado, validating communication between high-speed AHB masters and low-speed APB peripherals.

• Performed subsystem-level RTL verification against architectural requirements and verification plans to validate protocol compliance before integration.

• Verified 4 transaction signal groups - address, control, data, and handshake - across AHB/APB transactions using simulation and waveform debugging to identify timing and handshake mismatches. PROJECTS

AXI3 High-Speed Interconnect UVM Verification

• Built a UVM environment to verify AXI3 protocol behavior across 3 high-stress transaction classes - burst, unaligned, and out-of- order transactions.

• Developed constraint-driven tests targeting handshake behavior, burst operation, and data-transfer scenarios; performed simulation- driven validation, functional-coverage analysis, and waveform debugging to isolate protocol-level mismatches. Custom Processor Design & Verification

• Designed and implemented a pipelined custom processor incorporating an ALU, control FSM, instruction decode, branching logic, condition flags, and memory interfaces.

• Verified 5 core execution areas - instruction execution, control flow, branching, datapath behavior, and memory access - using directed instruction sequences, RTL simulation, and waveform debugging. PCIe Transaction Layer Verification

• Developed SystemVerilog verification scenarios across 3 PCIe transaction-layer areas - request/completion flow, posted and non- posted transactions, and basic error handling.

• Created protocol checkers and functional coverage points across 4 verification dimensions - packet fields, transaction ordering, completion behavior, and expected-response matching. EDUCATION

M.S., Electrical Engineering, San Jose State University May 2025 B.Tech., Electrical & Electronics Engineering, Pondicherry Technical University

Contact this candidate