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RTL Verification & FPGA VLSI Engineer resume in Chicago, IL - September 2026

Lipika Konena Agrahara Chandrakanth

[Bridgeport,Connecticut] [760-***-****] *************@*****.*** LinkedIn:

[https://www.linkedin.com/in/lipika-kc-4b2594253/?skipRedirect=true] VLSI Engineer RTL Design Design Verification SystemVerilog FPGA ASIC/SoC Static Timing Analysis SUMMARY

VLSI and...


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