RTL Verification & FPGA VLSI Engineer

Lipika Konena Agrahara Chandrakanth

[Bridgeport,Connecticut] [760-***-****] *************@*****.*** LinkedIn:

[https://www.linkedin.com/in/lipika-kc-4b2594253/?skipRedirect=true] VLSI Engineer RTL Design Design Verification SystemVerilog FPGA ASIC/SoC Static Timing Analysis SUMMARY

VLSI and Electrical Engineer with hands-on experience in RTL design support, design verification, simulation debugging, FPGA validation, waveform analysis, and block-level functional testing. Skilled in Verilog, SystemVerilog, digital logic design, finite state machines, test- bench development, timing concepts, reset behavior, and design documentation. Experienced in reviewing design specifications, writing clean RTL logic, preparing verification scenarios, debugging simulation mismatches, and documenting design observations for engineering review. Strong academic and project foundation in CMOS fundamentals, digital electronics, semiconductor devices, computer architec- ture, ASIC flow, and FPGA-based validation. Comfortable working with design, verification, validation, and hardware teams to clarify requirements, review issues, and close functional gaps before handoff. Well aligned for VLSI Engineer, Design Verification Engineer, RTL Engineer, FPGA Engineer, ASIC Design Engineer, and Electrical Engineer roles. TECHNICAL SKILLS

VLSI DESIGN & VERIFICATION

• RTL Design: Verilog, SystemVerilog, combinational logic, sequential logic, finite state machines, datapath logic, control logic, reusable RTL blocks

• Verification: Testbench development, directed testing, functional simulation, assertion concepts, coverage concepts, regression re- view, bug tracking

• ASIC Flow: RTL coding, lint review, synthesis-readiness checks, CDC concepts, low-power design concepts, static timing analysis concepts, design handoff support

• Debugging: Waveform analysis, simulation mismatch review, reset sequencing, clock behavior, signal tracing, timing-path review, corner-case validation

ELECTRICAL & DIGITAL HARDWARE

• Digital Electronics: Logic gates, flip-flops, counters, multiplexers, adders, registers, memory concepts, arithmetic circuits, state- machine design

• Semiconductor Concepts: CMOS fundamentals, MOSFET operation, propagation delay, setup and hold timing, power-delay trade- offs, PVT concepts

• FPGA & Hardware Validation: FPGA flow, RTL-to-FPGA validation, pin mapping concepts, clock and reset review, I/O behavior checks, board-level debug support

• Lab & Electrical Tools: Oscilloscope concepts, multimeter testing, schematic review, signal observation, test setup review, validation documentation

EDA TOOLS, SCRIPTING & DELIVERY

• EDA Tools: ModelSim, QuestaSim concepts, Xilinx Vivado, Intel Quartus concepts, Synopsys Design Compiler concepts, Cadence tool exposure

• Scripting & Platforms: Python basics, TCL scripting concepts, Linux commands, Git, Jira, Excel, simulation logs, technical notes

• Documentation: Design notes, verification plans, test scenarios, waveform screenshots, bug summaries, review comments, handoff documents

• Engineering Methods: Design reviews, peer review support, defect tracking, lab coordination, validation support, engineering status updates

WORK EXPERIENCE

VLSI Design & Verification Engineer — Synapse Design, a Quest Global Company, USA May 2025 – Present

• Support ASIC and SoC design-verification work by reviewing block-level specifications, understanding expected behavior, and convert- ing requirements into RTL and verification tasks.

• Develop and update Verilog and SystemVerilog RTL modules for digital logic blocks, finite state machines, reset handling, control paths, and interface-level signal behavior.

• Build directed test scenarios to validate reset behavior, normal operating flows, boundary conditions, invalid inputs, state transitions, and expected output responses.

• Debug simulation failures by reviewing waveforms, tracing signal transitions, checking state-machine behavior, and comparing ob- served results against design expectations.

• Assist with lint and synthesis-readiness reviews by checking coding style, incomplete assignments, latch risks, reset usage, unused signals, and logic paths that need clarification.

• Review clock and reset behavior across assigned blocks to identify unstable outputs, reset-sequencing issues, synchronization risks, and simulation mismatches before handoff.

• Work with design, verification, and physical-design teams to clarify open questions, review bug fixes, validate corrected behavior, and keep issue status updated.

• Maintain clean documentation for design notes, verification scenarios, bug summaries, waveform evidence, review comments, and handoff details for downstream teams.

• Participate in engineering discussions, code reviews, debug sessions, and status updates while keeping assigned tasks traceable through Jira and project documentation.

VLSI Engineer — MosChip Technologies, Hyderabad, India July 2023 – Aug 2024

• Supported digital design and verification activities involving RTL review, functional simulation, waveform debugging, FPGA validation support, and design documentation.

• Assisted with Verilog and SystemVerilog coding for small digital blocks, control logic, counters, multiplexers, finite state machines, register interfaces, and simple datapath modules.

• Prepared directed test cases to validate reset behavior, input combinations, output stability, control-flow transitions, and basic corner conditions against design expectations.

• Reviewed simulation waveforms to debug mismatches between expected and actual behavior, trace signal dependencies, and docu- ment findings for design review.

• Supported FPGA validation work by reviewing pin mapping assumptions, clock and reset behavior, I/O checks, timing constraints, and board-level signal observations.

• Helped review lint warnings, incomplete assignments, coding-style issues, combinational loops, reset concerns, and synthesis-readiness notes before module handoff.

• Collaborated with senior engineers to understand design specifications, update verification notes, confirm bug fixes, and prepare evidence for internal engineering reviews.

• Created project documentation including block-level notes, verification checklists, waveform screenshots, defect summaries, test re- sults, and handoff details.

• Built a practical understanding of ASIC design flow, verification discipline, debug methodology, timing concepts, and cross-team com- munication in semiconductor delivery.

KEY PROJECTS & LEADERSHIP

RTL Control Block Design and Functional Verification

• Designed and supported RTL logic for a control-oriented digital block using Verilog and SystemVerilog, with focus on FSM behavior, reset handling, input validation, and output sequencing.

• Prepared verification scenarios to validate state transitions, invalid input handling, reset recovery, output stability, and boundary behav- ior across simulation runs.

• Debugged failing simulations by reviewing waveforms, checking signal timing, tracing state-machine transitions, and correcting logic issues before engineering review.

• Documented design behavior, verification scope, waveform evidence, known limitations, and review notes so the block could be handed off with clear technical context.

Tech Stack: Verilog, SystemVerilog, QuestaSim/ModelSim, Waveform Debugging, FSM Design, RTL Review, Jira Impact: Improved confidence in block-level functionality before integration and reduced repeated debug effort during review cycles. FPGA-Based Digital Interface Validation

• Supported FPGA validation for a digital interface by reviewing input/output behavior, clock and reset assumptions, signal stability, and basic timing constraints.

• Assisted with test cases for interface transactions, reset recovery, edge conditions, and expected response checks during simulation and validation.

• Reviewed waveform captures, lab observations, pin behavior, and debug notes to identify mismatch areas between RTL simulation and hardware-level behavior.

• Prepared validation notes, issue summaries, and handoff material so design and validation teams could continue debugging with clear context.

Tech Stack: Verilog, Xilinx Vivado, FPGA Validation, Digital Interfaces, I/O Checks, Timing Constraints, Oscilloscope Concepts Impact: Connected simulation observations with hardware-level signal behavior and improved documentation for follow-up validation work. EDUCATION

University of Bridgeport Bridgeport, CT

Master of Science in Electrical Engineering

CERTIFICATIONS

• VLSI Design and Verification Training

• Verilog and SystemVerilog for Digital Design

• FPGA Design and Validation Fundamentals

• CMOS Digital Design and Static Timing Analysis Concepts

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