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Verilog, Python, RTL Design resume in San Jose, CA - March 2021
Parth Sathe
***********.**@*****.*** San Jose, CA 95126 +1-669-***-****
LinkedIn: https://www.linkedin.com/in/parthsathe7/ EDUCATION
San Jose State University, San Jose, CA, USA - GPA: 3.8/4.0 Jan 2020-May 2021 Master of Science in Electrical Engineering
Coursework - Semiconductor Device...
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