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Engineer Design resume in San Francisco, CA - September 2015
Neelima Ramisetti
**** ******* **, **** *********, IN.
Email: **********@*****.***
Ph # 972-***-****.
Summary:
●ASIC/FPGA Verification: Over 10 years of experience in verification. Languages used: System Verilog, UVM, Vera, Specman.
●ASIC Design: Over 3 years experience in RTL coding,...
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