Engineer Design

Neelima Ramisetti

**** ******* **, **** *********, IN.

Email: **********@*****.***

Ph # 972-***-****.

Summary:

●ASIC/FPGA Verification: Over 10 years of experience in verification. Languages used: System Verilog, UVM, Vera, Specman.

●ASIC Design: Over 3 years experience in RTL coding, simulation, synthesis, and verification of ASICs. Design and Synthesis of FPGAs using Xilinx Virtex tools

●Verilog & VHDL: Design, analysis, simulation, synthesis and timing analysis.

●Strong knowledge of Ethernet, SONET/SDH protocols and Digital Signal processing.

TECHNICAL SKILLS:

HDLs: VHDL, Verilog

Verification: Specman, System Verilog, Vera, UVM

Simulators: ModelSim, Verdi, Simvision, VCS

Synthesis: Xilinx ISE, Synopsys Design Compiler, Cadence

Programming Skills: C, C++

Scripting Perl, TCL

Work Experience:

Sunburst / Verilab, San Jose 8/2015

System Verilog UVM Training

Attended advanced System Verilog UVM training to learn latest UVM techniques. Explored and learnt OVM/UVM resources like UVM factory and constructors, UVM scoreboard architecture, UVM virtual sequencers, and UVM macros.

Intel, Chicago 5/2014 – 11/2014

ASIC Verification Consultant

Responsible for block-level and top-level verification tasks of LTE Inner Receiver ASIC.

Performed RTL verification using VHDL and C testbench. Worked with Matlab to create new stimuli for the RTL testbench. Performed debugging on Matlab code to identify test model issues.

Created new testcases, modified existing ones and debugged issues using VCS and Synopsys DVE environment. Worked with designers to help fix errors in VHDL code. Modified existing PERL files to add test suites to the regression.

Performed FPGA testing on the design emulated on Virtex6 FPGA boards. Ran several tests and helped reproduce issues on top-level RTL simulation and debug issues.

Western Digital 6/2011 – 12/2013

ASIC Verification Consultant

●Responsible for verification tasks of Hard disk Drive controller ASIC verification. Entered the team and immediately contributed by modifying existing Specman tests and legacy testbench code to add new features to checkers and monitors.

●Created various sequences and monitors to perform Ecclog feature and Channel error testing for different chips. Performed regression testing using Specman Vplanner, debugging, log results and fixing regression issues.

●Also responsible for maintaining verification environments that interact with both LSI and Marvell channel models (designed in System Verilog), create checkers, use Irun environment to simulate and execute tests in NCSIM/SimVision.

●Performed coverage analysis and updated Vplan items to assess coverage. Wrote and updates various cover structs for functional coverage based on coverage review from Specman Eplanner.

●Active contributor on team driving Universal Reuse Methodology (UVM) standardization based on Specman. Developed interface and monitor components based on virtual sequences for system-level tests.

Qualcomm Inc 7/2010 – 6/2011

ASIC Design & Verification Engineer

●Responsible for verification of Tabla DSP ASIC. Worked to verify various IIR/FIR filters and other Signal processing blocks present in the Tabla Codec.

●Verified Interrupt controller and Tabla controller blocks using Vera testbench.

●Wrote System Verilog assertions to prove different parts of the design. Used Jasper formal tool to verify the DUT.

●Converted a testbench written in Vera to System Verilog. Worked on developing block-level testcases in System Verilog.

●Responsible for running regressions and collecting coverage. Attended System Verilog OVM/UVM training and was responsible for planning TB architecture in UVM.

Fujitsu Network Communications Inc., Richardson, TX 5/2006-4/2010

ASIC/FPGA Design & Verification Engineer

Packet Engine FPGA

●Responsible for design and verification of Packet Engine FPGA that provides Ethernet Over Sonet functionality including Virtual Concatenation. This FPGA was targeted for a Virtex5-LX220 Speed Grade device. Performed RTL coding (Verilog) of the complicated bit-oriented protocol DS3 over SONET.

●Developed an entire block level testbench for the DS3 block in System Verilog. This testbench was equipped with all features like agents, BFMs, generators, checkers, scoreboards, and monitors.

●Developed Specman testbench for Ethernet over E3 based on e Reuse Methodology (eRM). This testbench tests the transport of an E3 frame over SDH Tu-3 payload.

Muxponder FPGA

●Involved in the system-level and block-level verification of Muxponder FPGA that performs Ethernet LAN over SONET adaptation for different data rates.

●Created and executed verification test plans for testing different data modes: Ethernet, Fibre Channel, 100FX, GFPT and SONET.

●Created detailed block-level testbenches using e-code and Specman for testing data implemented protocols like GFPT and Fibre Channel. Merged these testbenches with top-level to run regressions suites that were created using PERL/TCL on the entire device under test.

●Used Specman Profiler to improve simulation speed and performed coverage in “e” language. Helped to train some junior verification engineers in learning the eVM and eRM methodology.

SPS48 Framer ASIC

●Helped in the design and verification of OC-48 SONET Framer ASIC. Verification testbenches were developed using Verilog, E-code and Perl Scripts. Created and automated testcases using e-code in Specman Environment.

●Debugged Verilog RTL using Simvision to identify the faulty region before reporting a defect. Performed regression and top-level tests on the entire design.

White Rock Networks(Acquired by Juniper) Richardson, TX 4/2003-4/2006 ASIC Design Engineer

●Involved in the design and verification of a 10 GBps SONET Framer ASIC. Wrote and executed verification test plans. Created and automated testcases using Specman and RAVE.

●Created configurations and behavioral models in VHDL to enhance simulation speed. Verified the design by simulating it in ModelSim and debugged RTL to identify the faulty region before reporting a defect.

●Performed regression tests and top-level tests on the entire design. Scripts written in PERL are used to perform automated cyclic runs on the DUT.

EDUCATION:

Master of Science in Electrical Engineering- Digital Systems, December 2003

University of Texas at Dallas, Richardson, Texas.

Bachelors in Electronics and Communication Engineering - Osmania University, India.

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