| Resume alert | Resumes 111 - 120 of 311 |
Engineer Project
New Delhi, DL, India
... DESIGANATION: VLSI Engineer Project1: Verification of SPI Master Slave core using Wishbone Brief Description: The test bench architecture is based on the Universal Verification Methodology (UVM) which enables the creation of highly reusable and ... - 2015 Dec 10
... DESIGANATION: VLSI Engineer Project1: Verification of SPI Master Slave core using Wishbone Brief Description: The test bench architecture is based on the Universal Verification Methodology (UVM) which enables the creation of highly reusable and ... - 2015 Dec 10
HR manager, Admin, Project Manager, NGO
New Delhi, DL, India
... EDUCATIONAL QUALIFICATION : EXAMINATION DISCIPLINE SCHOOL/COLLEGE BOARD/UNIVERSITY YEAR PASSING PERCENTAGE of MARKS M.Tech VLSI Design Mewar Institute, Ghaziabad Mewar University, Rajasthan 2015 69.9 B.Tech Electronics & Communication Laxmi Devi ... - 2015 Nov 23
... EDUCATIONAL QUALIFICATION : EXAMINATION DISCIPLINE SCHOOL/COLLEGE BOARD/UNIVERSITY YEAR PASSING PERCENTAGE of MARKS M.Tech VLSI Design Mewar Institute, Ghaziabad Mewar University, Rajasthan 2015 69.9 B.Tech Electronics & Communication Laxmi Devi ... - 2015 Nov 23
Engineer Power
Noida, UP, India
... The values were modified and controlled in order to optimize plant growth and maximize yield Role: Wrote the key to operate the microcontroller KeyLearning: Embeded C, Steper Motor working, LED working Title: BCD Adder in VLSI using Verilog HDL ... - 2015 Nov 19
... The values were modified and controlled in order to optimize plant growth and maximize yield Role: Wrote the key to operate the microcontroller KeyLearning: Embeded C, Steper Motor working, LED working Title: BCD Adder in VLSI using Verilog HDL ... - 2015 Nov 19
Project Training
New Delhi, DL, India
... ACADEMIC PROJECT UNDERTAKEN Minor Project: Project: UART (VLSI), Simulation on Xining tools Team Size: 4 Description: In this minor project we learnt about the transfer of data. Extra curricular activity:- Runner Up in Robotics competition Runner Up ... - 2015 Nov 16
... ACADEMIC PROJECT UNDERTAKEN Minor Project: Project: UART (VLSI), Simulation on Xining tools Team Size: 4 Description: In this minor project we learnt about the transfer of data. Extra curricular activity:- Runner Up in Robotics competition Runner Up ... - 2015 Nov 16
Windows, Linux, Unix, MDM Etc.
Gurgaon, HR, India
... Analog Communication, Digital Communication, Satellite communication, Optical Communication System and Network administration, Antenna & Wave Propagation, VLSI, CMOS. Computer Networking, Wireless And Mobile Computing Mobile Communication, EMM ... - 2015 Nov 16
... Analog Communication, Digital Communication, Satellite communication, Optical Communication System and Network administration, Antenna & Wave Propagation, VLSI, CMOS. Computer Networking, Wireless And Mobile Computing Mobile Communication, EMM ... - 2015 Nov 16
Design Engineer
Faridabad, HR, India
... To be a part of research and project team as an Intern for Six Months (Dec’15/ Jan’16 - May’16/ Jun’16) duration in VLSI Design PROFESSIONAL SYNOPSIS 1.5 months of training experience in Functional Verification using SystemVerilog in Mentor ... - 2015 Nov 12
... To be a part of research and project team as an Intern for Six Months (Dec’15/ Jan’16 - May’16/ Jun’16) duration in VLSI Design PROFESSIONAL SYNOPSIS 1.5 months of training experience in Functional Verification using SystemVerilog in Mentor ... - 2015 Nov 12
electronics and communication engineer
New Delhi, DL, India
... Mac OS X Interest/Hobbies VLSI, SMT Sensors and Electronics, Optics, Virtual Computing, Networking, Medical Electronics, Moral Technology, Imaginative Technology, Cognitive Radio, Solar Technology. Writing, Introspection, Travelling Short Distances. - 2015 Oct 31
... Mac OS X Interest/Hobbies VLSI, SMT Sensors and Electronics, Optics, Virtual Computing, Networking, Medical Electronics, Moral Technology, Imaginative Technology, Cognitive Radio, Solar Technology. Writing, Introspection, Travelling Short Distances. - 2015 Oct 31
Design Engineering
New Delhi, DL, India
... OBJECTIVE Being a post graduate in VLSI design, I am seeking for a position in your company that requires applying my analytical skills in the field of design and verification. EDUCATION Pursuing 6 months training on verification using System ... - 2015 Oct 30
... OBJECTIVE Being a post graduate in VLSI design, I am seeking for a position in your company that requires applying my analytical skills in the field of design and verification. EDUCATION Pursuing 6 months training on verification using System ... - 2015 Oct 30
RTL design and verification
New Delhi, DL, India
UJJWAL KAUSHIK 882-***-**** Email: acrz65@r.postjobfree.com Career Objective To work enthusiastically in a semiconductor industry which would help me follow my passion in VLSI domain and help to get the best out of me and prove myself as an ... - 2015 Oct 07
UJJWAL KAUSHIK 882-***-**** Email: acrz65@r.postjobfree.com Career Objective To work enthusiastically in a semiconductor industry which would help me follow my passion in VLSI domain and help to get the best out of me and prove myself as an ... - 2015 Oct 07
Project Security
New Delhi, DL, India
... Academic Credentials: Qualification College /Board Year of passing Percentage 63 % ( 3nd Semester) M.Tech (VLSI) SHARDA UNIVERSITY 2013-15 (Pursuing) B.Tech(Electronic And MACET,patnna/ Magadh 2007-12 70.67% Communication) University, Bihar 12th R.P ... - 2015 Oct 07
... Academic Credentials: Qualification College /Board Year of passing Percentage 63 % ( 3nd Semester) M.Tech (VLSI) SHARDA UNIVERSITY 2013-15 (Pursuing) B.Tech(Electronic And MACET,patnna/ Magadh 2007-12 70.67% Communication) University, Bihar 12th R.P ... - 2015 Oct 07