| Resume alert | Resumes 81 - 90 of 448 |
Electrical Engineering Operator
Livermore, CA
... Education California State Polytechnic University, Pomona June 2018 Major: Electrical Engineering GPA: 3.76 Graduated Magna cum Laude Membership in IEEE Focus: Extensive lab work and coursework in Verilog, lab work and coursework in microprocessors, ... - 2018 Jul 20
... Education California State Polytechnic University, Pomona June 2018 Major: Electrical Engineering GPA: 3.76 Graduated Magna cum Laude Membership in IEEE Focus: Extensive lab work and coursework in Verilog, lab work and coursework in microprocessors, ... - 2018 Jul 20
Student Assistant
Union City, CA
... My Duty: To create a single language compiler(System Verilog) that targets both FPGA and CPU. Tools Used : Lex/Yacc, LLVM, SystemVerilog/Verilog( hardware languages) Supervisor : Prof. James Tandon, CSU East Bay (ac5920@r.postjobfree.com) Student ... - 2018 Jul 16
... My Duty: To create a single language compiler(System Verilog) that targets both FPGA and CPU. Tools Used : Lex/Yacc, LLVM, SystemVerilog/Verilog( hardware languages) Supervisor : Prof. James Tandon, CSU East Bay (ac5920@r.postjobfree.com) Student ... - 2018 Jul 16
Electrical Engineer Engineering
San Jose, CA
... TECHNICAL SKILL SET Languages: Verilog, MATLAB, embedded C, C, C++, Tcl (Scripting) Tools and skills: LabView, MATLAB, Simulink, PCB design, Synopsys EDA tools-VCS, Design Compiler and IC compiler, TetraMax ATPG, Altium, Logisim, Proteus, OrCAD, ... - 2018 Jul 13
... TECHNICAL SKILL SET Languages: Verilog, MATLAB, embedded C, C, C++, Tcl (Scripting) Tools and skills: LabView, MATLAB, Simulink, PCB design, Synopsys EDA tools-VCS, Design Compiler and IC compiler, TetraMax ATPG, Altium, Logisim, Proteus, OrCAD, ... - 2018 Jul 13
Engineer Design
San Jose, CA
... Core strengths in: Verification Partitioning and Development Flow Directed and Coverage Driven Random Verification Flow I/O Protocols and Controllers Verification TECHNICAL SKILLS Methodologies and Languages UVM,System Verilog (SV), Verilog, System ... - 2018 Jul 12
... Core strengths in: Verification Partitioning and Development Flow Directed and Coverage Driven Random Verification Flow I/O Protocols and Controllers Verification TECHNICAL SKILLS Methodologies and Languages UVM,System Verilog (SV), Verilog, System ... - 2018 Jul 12
CAD/EDA /PDK development/Physical design engineer
Campbell, CA
... SKILL AREAS: TCL, Perl, Shell, Verilog, VHDL, Skill, ocean, Lisp, awk, sed, grep, C, Assembly 88/86/68, Python TOOLS USED: Synopsys, Cadence, Mentor, Agilent/Keysight, Silicon Frontline, Design Sync, Clio Soft, Nassda, Verilog,bda SYSTEMS USED: Sles ... - 2018 Jun 20
... SKILL AREAS: TCL, Perl, Shell, Verilog, VHDL, Skill, ocean, Lisp, awk, sed, grep, C, Assembly 88/86/68, Python TOOLS USED: Synopsys, Cadence, Mentor, Agilent/Keysight, Silicon Frontline, Design Sync, Clio Soft, Nassda, Verilog,bda SYSTEMS USED: Sles ... - 2018 Jun 20
Engineer Microsoft Office
San Jose, CA
... and Simulation: Altium, Orcad, Protel, Proteus, PSpice, AutoCAD PLC, Allen Bradley, SIMATIC, Ladder, Text Instructure C, VeriLog, Python, C++ Languages Graphic Unit Interface (GUI) LabVIEW, MATLAB Code Vision and Arduino Robotic Controller, ... - 2018 Jun 19
... and Simulation: Altium, Orcad, Protel, Proteus, PSpice, AutoCAD PLC, Allen Bradley, SIMATIC, Ladder, Text Instructure C, VeriLog, Python, C++ Languages Graphic Unit Interface (GUI) LabVIEW, MATLAB Code Vision and Arduino Robotic Controller, ... - 2018 Jun 19
Electrical Engineer Design
San Jose, CA
Educational Qualification: Masters in Electrical engineering (WNEU): 3.86 GPA (December, 2017) Bachelors of Engineering (BNMIT): 3.1 GPA Skills/Tools: Languages: Verilog, Python. Simulation Tools: Cadence OrCAD Capture, Allegro, Xilinx Vivado, SOC ... - 2018 May 24
Educational Qualification: Masters in Electrical engineering (WNEU): 3.86 GPA (December, 2017) Bachelors of Engineering (BNMIT): 3.1 GPA Skills/Tools: Languages: Verilog, Python. Simulation Tools: Cadence OrCAD Capture, Allegro, Xilinx Vivado, SOC ... - 2018 May 24
Design Engineer Electrical Engineering
San Jose, CA
... Coursework ASIC CMOS Design, Digital Logic Design and Synthesis, System-On-Chip Design and Verification using System Verilog, Advanced Computer Architecture, Digital System Verification using UVM Skills Programming: C, Python, Perl, Verilog, ... - 2018 May 20
... Coursework ASIC CMOS Design, Digital Logic Design and Synthesis, System-On-Chip Design and Verification using System Verilog, Advanced Computer Architecture, Digital System Verification using UVM Skills Programming: C, Python, Perl, Verilog, ... - 2018 May 20
Engineering Electrical
San Jose, CA
... Skill Sets: Languages: C, Python, C++, Verilog, Shell Scripting. Design & Hands-On Experience: Git, GitHub, Beagle Bone Black, Arduino Uno, Raspberry Pi 3, ESP8266, OpenMP, OpenACC, OpenCL, MPI, Tensorflow, Keras, Home Automation, Microsoft Office. ... - 2018 May 18
... Skill Sets: Languages: C, Python, C++, Verilog, Shell Scripting. Design & Hands-On Experience: Git, GitHub, Beagle Bone Black, Arduino Uno, Raspberry Pi 3, ESP8266, OpenMP, OpenACC, OpenCL, MPI, Tensorflow, Keras, Home Automation, Microsoft Office. ... - 2018 May 18
Software Engineer State University
San Jose, CA
... RS-485 • Matlab, Ada, Satellite Tool Kit (STK), SCL, and SCS-21/STSS • PERL, Python, TCL/TK, Unix shell (TCSH/CSH) scripting, and Verilog • GUI development using XML, X-Windows/Motif, MFC, Visual Studio C++/C#, Qt/QML, and Kinesix Sammi • Clearcase ... - 2018 Apr 22
... RS-485 • Matlab, Ada, Satellite Tool Kit (STK), SCL, and SCS-21/STSS • PERL, Python, TCL/TK, Unix shell (TCSH/CSH) scripting, and Verilog • GUI development using XML, X-Windows/Motif, MFC, Visual Studio C++/C#, Qt/QML, and Kinesix Sammi • Clearcase ... - 2018 Apr 22