| Resume alert | Resumes 91 - 100 of 161 |
Information Technology Engineering
Chennai, TN, India
... Technical skills: Embedded Design in Arduino Uno Board Interfacing with FPGA in Zed Board Zynq (Verilog Code) PCB Design using DIP Trace software tools Personal Profile: Punctual, reliable and highly responsible for any tasks assigned. Possesses ... - 2016 Nov 12
... Technical skills: Embedded Design in Arduino Uno Board Interfacing with FPGA in Zed Board Zynq (Verilog Code) PCB Design using DIP Trace software tools Personal Profile: Punctual, reliable and highly responsible for any tasks assigned. Possesses ... - 2016 Nov 12
Engineering Design
Chennai, TN, India
... Domain: Low power B.E - “DESIGN AND IMPLEMENTATION OF HIGH SPEED OFDM TRANCEIVER ON FPGA” Description OFDM has been proposed to efficient modulation. To high speed digital audio broadcast, to high-speed wireless data communications. Domain: ... - 2016 Nov 07
... Domain: Low power B.E - “DESIGN AND IMPLEMENTATION OF HIGH SPEED OFDM TRANCEIVER ON FPGA” Description OFDM has been proposed to efficient modulation. To high speed digital audio broadcast, to high-speed wireless data communications. Domain: ... - 2016 Nov 07
Microsoft Office Engineer
Chennai, TN, India
... :Windows XP, Windows 7 Applications : Microsoft Office Software tools :MATLAB, Xilinx ISE Area of interest: Wireless communication Wireless sensor networks Project profile: Implementation Of Encryption And Decryption Algorithm Based On AES In FPGA. ... - 2016 Oct 30
... :Windows XP, Windows 7 Applications : Microsoft Office Software tools :MATLAB, Xilinx ISE Area of interest: Wireless communication Wireless sensor networks Project profile: Implementation Of Encryption And Decryption Algorithm Based On AES In FPGA. ... - 2016 Oct 30
VLSI Developer
Chennai, TN, India
... Contribution Developed IEEE paper Team Size/Duration Independently handled RTL coding using VHDL /6 months Languages/Tools VHDL, Xilinx ISE 14.2 UG Project RNS to Binary converter for Moduli sets {2n+1, 2n, 2n-1} in FPGA Design Domain VLSI ... - 2016 Oct 27
... Contribution Developed IEEE paper Team Size/Duration Independently handled RTL coding using VHDL /6 months Languages/Tools VHDL, Xilinx ISE 14.2 UG Project RNS to Binary converter for Moduli sets {2n+1, 2n, 2n-1} in FPGA Design Domain VLSI ... - 2016 Oct 27
Inplant Training, Project Team Leader
Chennai, TN, India
... board [2010] with aggregate of 78 from Sree Narayana Guru Matriculation Higher secondary School,Kottar PROJECT DETAILS • FPGA based Speed Control of Brushless DC motor Using Digital PWM Technique Description : used to control the speed of the BLDC ... - 2016 Sep 30
... board [2010] with aggregate of 78 from Sree Narayana Guru Matriculation Higher secondary School,Kottar PROJECT DETAILS • FPGA based Speed Control of Brushless DC motor Using Digital PWM Technique Description : used to control the speed of the BLDC ... - 2016 Sep 30
Sales Service
Chennai, TN, India
... Engineering Project: A partial reconfiguration based approach for frequency synthesis using FPGA” Broad Based Skills: Team Building Leadership Mentor for the team Ability to work independently and as part of a team. Cost Saving initiatives Creative ... - 2016 Aug 27
... Engineering Project: A partial reconfiguration based approach for frequency synthesis using FPGA” Broad Based Skills: Team Building Leadership Mentor for the team Ability to work independently and as part of a team. Cost Saving initiatives Creative ... - 2016 Aug 27
Engineering Technology
Chennai, TN, India
... The low density parity check plays a vital role in the resilient of FPGA. Soft error due to bit miss is detected using built in self-test and overcome by the error correction method using Low Density Parity Check. This helps in reducing the ... - 2016 Aug 10
... The low density parity check plays a vital role in the resilient of FPGA. Soft error due to bit miss is detected using built in self-test and overcome by the error correction method using Low Density Parity Check. This helps in reducing the ... - 2016 Aug 10
Project School
Chennai, TN, India
... FINAL YEAR PROJECT: FPGA implementation of ADVANCED ENCRYPTION STANDARD with optimized mix column technique to reduce the number of logic gates and for improving the architecture. The enhanced Mix-Column transformation with S-Box is to reduce the ... - 2016 Jun 30
... FINAL YEAR PROJECT: FPGA implementation of ADVANCED ENCRYPTION STANDARD with optimized mix column technique to reduce the number of logic gates and for improving the architecture. The enhanced Mix-Column transformation with S-Box is to reduce the ... - 2016 Jun 30
vhdl,verilog,c,embedded c
Chennai, TN, India
... Participated in the workshop on “Image processing framework using FPGA”. 5)Implant Training Three days in A-Bond Strands Private Limited, Chennai during 2011. One week in ‘On Line Data Entry Of Wagons’, Chennai during 2011. One day visited ISRO, ... - 2016 Jun 21
... Participated in the workshop on “Image processing framework using FPGA”. 5)Implant Training Three days in A-Bond Strands Private Limited, Chennai during 2011. One week in ‘On Line Data Entry Of Wagons’, Chennai during 2011. One day visited ISRO, ... - 2016 Jun 21
Completed M.Tech in Power Electronics and Drives with VIT University
Chennai, TN, 600122, India
... Participated in One day national level workshop on “PWM Implementation using FPGA for Power Converters”. SKILLS: a) Software: S.No Software Name Version 1 MS Office 2007,2010,2013 2 MATLAB 2009b, 2010b,2012b,2014a 3 ORCAD,PSPICE 9 LITE EDITION 4 ... - 2016 May 07
... Participated in One day national level workshop on “PWM Implementation using FPGA for Power Converters”. SKILLS: a) Software: S.No Software Name Version 1 MS Office 2007,2010,2013 2 MATLAB 2009b, 2010b,2012b,2014a 3 ORCAD,PSPICE 9 LITE EDITION 4 ... - 2016 May 07