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VLSI Developer

Location:
Chennai, Tamil Nadu, India
Salary:
35,000 per month
Posted:
October 27, 2016

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Priyanka A.

#**, *********** ******,

Varatharajapuram (Uppilipalayam post),

Coimbatore - 641015.

Mob No. :+91-897*******, 741-***-****

Email ID : acw9xl@r.postjobfree.com

Career Objective

To pursue a job that invokes immense challenge ensuring a continuous process of learning, paving way to efficient productivity and team work. Professional Summary

I am currently working in Techmindz as VLSI Developer of 1 year & 3 months of Experience.

Coordinator for RTL Design, MATLAB and Power Electronics.

My Project Title#1 got University 1st Rank in Msc.VLSI.

Good working knowledge in VLSI Design.

Good Working Experience in Xilinx ISE,ModelSim, and Tanner EDA.

Experience in writing RTL models in Verilog HDL, VHDL and Test benches in Verilog.

Good experience in Formal Verification, Functional and Gate-level verification.

Basic knowledge on System Verilog, Perl and AMBA - APB,AXI,AHB.

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Academic Chronicle

M.E -VLSI Design( 2013-2015)-CGPA- 8.0 from Kalaignar Karunanidhi Institute of Technology (KIT), Coimbatore.

B.E- ECE (2009-2013) -CGPA – 7.43 from Dr.N.G.P.Institute of Technology (Dr.N.G.P.IT), Coimbatore.

HSC. (2007-2009) – 79% from P.S.G.G.Kanya Guru Kulam Higher Secondary School, Coimbatore, Tamil Nadu.

SSLC. (2006-2007) - 82% from P.S.G.G.Kanya Guru Kulam Higher Secondary School, Coimbatore, Tamil Nadu.

Organization scan

Working as a VLSI Developer in Techmindz, from July 2015 to Till Date. Technical Skills

Programming Languages

Verification Languages

Simulation Tools

Knowledge

Script

Operating Systems

Bus Protocol

VHDL, Verilog HDL.

Basic System Verilog

Xilinx ISE,ModelSim, and Tanner EDA.

RTL Coding, FSM based design, Gate level Simulation Basic Perl

Windows / Linux.

Basic of AMBA - APB,AXI,AHB

2

PG & UG Project

PG Project Multifunctional Digital Timing Synchronization For Wireless Body Area Network(WBAN)

Domain VLSI

Description WBAN transceiver consists of Transmitter and Receiver Baseband. In each of baseband consisting of Hamming Code, Interleaver, Scrambler. The Transmitter baseband analysis both adders CLA and CSLA and comparatively a low power and less gate count achieved in SQRT CSLA. This SQRT CSLA baseband had low-complexity architecture to achieve satisfactory performance in power and transmission rate consider on the gate count. Contribution Developed IEEE paper

Team

Size/Duration

Independently handled RTL coding using VHDL /6 months Languages/Tools VHDL, Xilinx ISE 14.2

UG Project RNS to Binary converter for Moduli sets {2n+1, 2n, 2n-1} in FPGA Design Domain VLSI

Description The Conversion from residue to binary form which uses CRT (Chinese Remainder Theorem) for the moduli sets (2n, 2n+1, 2n-1) using Carry Save Adder followed by Carry Propagate Adder. It leads to reduce the yield of design such as area cost, delay and power consumption. Contribution Developed IEEE paper

Team

Size/Duration

5/6 months

Languages/Tools VHDL, Xilinx ISE 14.2

Project Works

Project title #1 Low Power and Area-Efficient Shift Register using Pulsed Latch Description The proposed PIPO Shift Register reduces the number of delayed pulsed clock signals significantly and also reduces the number of latch over existing SISO Shift Register . This Project includes RTL coding of Delayed pulsed clock generator, pulsed latch, 5 & 4 -Sub Shift Register, PIPO Shift Register, SISO Shift Register, which reduce the area,time and power consumption over the SISO shift register.

Contribution Developed IEEE paper

Role

&Responsibilities

Independently handled RTL coding using VHDL

Languages/Tools VHDL, Xilinx ISE 14.7,Tanner EDA

Project title #2 High Speed and Energy Efficient Carry Skip Adder Operating under a Wide Range of Supply Voltage Level

Description The Proposed Hybrid CSKA based on Ladner Fischer Adder over Existing Brent-Kung Adder, which has less area leads to decrease in the number of stages as reduce time and power consumption .This Project includes RTL coding of conventional structure of CSKA with MUX, CL-CSKA structure with AOI and OAI, Proposed Hybrid CSKA with Ladner Fischer and Brent –Kung Adder.

3

Contribution Developed IEEE paper

Role

&Responsibilities

Independently handled RTL coding using VHDL

Languages/Tools VHDL, Xilinx ISE 14.7

Papers Presented

Presented a paper titled ‘Multifunctional Digital Timing Synchronization for Wireless Body Area Network’ in International Conference ICIIECS’15 conducted by Karapagam college of Engineering and technology, Coimbatore.

Presented a paper titled ‘Design of Data Processing Based on Folded Tree for Wireless Sensor Nodes’ in International Conference ICC’15 conducted by Kalaignar Karunanidhi college of Engineering and technology, Coimbatore. Achievements

Best Volunteer Awarded for Techno blast symposium by Dr.N.G.P.IT in 2012.

Youth Leadership Awarded for 19th Consecutive Ryla by Rotary Club of Coimbatore Texcity in 2008.

Got 3rd prize for Project of Interrelation between Insects and Flowers (Butterflies) by Salim Ali Center for Ornithology and Natural History (SACON) -Nature club in 2005.

Got 3rd prize in Annual Fuction for Group dances by KIT in 2014.

Got 1st prize in Annual Sports Meet for 400mtsRelay by Dr.N.G.P IT in 2011.

Got 2 ndprize in Annual Sports Meet for 400mtsRelay by Dr.N.G.P IT in 2010.

Got 3rd prize in Indian Karate Academy for Girls Karate by Oxford School in 2001. Personal Details

Father’s Name

Nationality

Date of Birth

Gender

Marital Status

Languages Known

Permanent Address

Ammasaiappan

Indian

26/04/1991

Female

Single

English, Tamil

60, Jayaprakesh Street,

Varatharajapuram (Uppilipalayam post),

Coimbatore -641015.

I hereby declare that the above-furnished details are true and correct to the best of my knowledge.



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