| Resume alert | Resumes 1 - 10 of 49 |
Electrical Engineer
Washougal, WA
... RTL design/verification experience Expertise in Verilog, VHDL and SystemVerilog RTL design. Micro-architecture, implementation and testing of custom IP blocks Third party IP integration and verification (UPF, IP-Xact register and document generation ... - Sep 10
... RTL design/verification experience Expertise in Verilog, VHDL and SystemVerilog RTL design. Micro-architecture, implementation and testing of custom IP blocks Third party IP integration and verification (UPF, IP-Xact register and document generation ... - Sep 10
Design Engineer Engineering
Portland, OR
... Became the go-to guru for System Verilog implementation questions and synchronization issues. • Was a primary author for the department’s methodology guide, including authoring much of the coding guidelines and RDC (Reset Domain Crossing) chapters, ... - Jun 10
... Became the go-to guru for System Verilog implementation questions and synchronization issues. • Was a primary author for the department’s methodology guide, including authoring much of the coding guidelines and RDC (Reset Domain Crossing) chapters, ... - Jun 10
Software Engineer C#
Gresham, OR
... Bourquin Portland, OR · 503-***-**** · ad3xqi@r.postjobfree.com Technology: Development: Eclipse, Xcode, Visual Studio, RAD Studio, Android Studio, Eagle (PCB) Language: Objective-C, Java, C, C++, C# OOD/OOP, Python, Verilog, VHDL, LVS, NLE Hardware ... - Feb 26
... Bourquin Portland, OR · 503-***-**** · ad3xqi@r.postjobfree.com Technology: Development: Eclipse, Xcode, Visual Studio, RAD Studio, Android Studio, Eagle (PCB) Language: Objective-C, Java, C, C++, C# OOD/OOP, Python, Verilog, VHDL, LVS, NLE Hardware ... - Feb 26
Circuit Design A Senior
Portland, OR
... Wrote and debugged the Verilog code using ModelSim ●Synthesized and implemented the Verilog code. Generated and downloaded the bitstream to FPGA using Vivado software ●Conducted RF simulation to characterize the S-parameters, noise figure, gain, ... - Jan 20
... Wrote and debugged the Verilog code using ModelSim ●Synthesized and implemented the Verilog code. Generated and downloaded the bitstream to FPGA using Vivado software ●Conducted RF simulation to characterize the S-parameters, noise figure, gain, ... - Jan 20
HFSS,VERILOG,PYTHON
Hillsboro, OR
... with Verilog, Microprocessors and interfacing, RF Cellular communications, Optical communications, Satellite communications, Antennas and wave propagation, Linear integrated circuits, Electromagnetic waves, Electrical Circuit Theory and Analysis. ... - Jan 08
... with Verilog, Microprocessors and interfacing, RF Cellular communications, Optical communications, Satellite communications, Antennas and wave propagation, Linear integrated circuits, Electromagnetic waves, Electrical Circuit Theory and Analysis. ... - Jan 08
Software Engineer Machine Learning
Portland, OR
... Documentation Application Development Technical Skills Programming Languages: Java, Python, SQL, JavaScript, HTML, CSS, Verilog, VHDL Development Tools: Git, Jira, Node.js, Heroku, Jest, Jenkins Cloud and Infrastructure: AWS Machine Learning and ... - Jan 04
... Documentation Application Development Technical Skills Programming Languages: Java, Python, SQL, JavaScript, HTML, CSS, Verilog, VHDL Development Tools: Git, Jira, Node.js, Heroku, Jest, Jenkins Cloud and Infrastructure: AWS Machine Learning and ... - Jan 04
A Team Electrical Engineering
Newberg, OR
... SKILLS Known Software Languages: Python, Java, C, Verilog, Arduino, Matlab, SwiftUI. Proficient in circuit design using softwares like multisim. EDUCATION George Fox University — Electrical Engineering 2021 - 2025 3.8 GPA, Student Athlete, ... - 2023 Nov 29
... SKILLS Known Software Languages: Python, Java, C, Verilog, Arduino, Matlab, SwiftUI. Proficient in circuit design using softwares like multisim. EDUCATION George Fox University — Electrical Engineering 2021 - 2025 3.8 GPA, Student Athlete, ... - 2023 Nov 29
Ic Design Engineer
Portland, OR
... feedback technique for 1/f flicker noise up-conversion suppression in SiGe:C BiCMOS process Skills CAD tools: MATLAB, Verilog/VerilogA, Synopsys Hspice, Cadence tools (Spectre, ADE/Virtuoso XL), Cadence EMX, Agilent ADS/Momentum/FEM, Ansys HFSS, ... - 2023 Nov 07
... feedback technique for 1/f flicker noise up-conversion suppression in SiGe:C BiCMOS process Skills CAD tools: MATLAB, Verilog/VerilogA, Synopsys Hspice, Cadence tools (Spectre, ADE/Virtuoso XL), Cadence EMX, Agilent ADS/Momentum/FEM, Ansys HFSS, ... - 2023 Nov 07
Quality Assurance & Test Engineering
Portland, OR
... FPGA Audio Recorder, Arizona State University 5/2020 • Wrote Verilog firmware to control Xilinx NEXYS FPGA. Firmware implemented audio recording and playback system, where it took user input from switches. • Firmware deserialized microphone input, ... - 2023 May 01
... FPGA Audio Recorder, Arizona State University 5/2020 • Wrote Verilog firmware to control Xilinx NEXYS FPGA. Firmware implemented audio recording and playback system, where it took user input from switches. • Firmware deserialized microphone input, ... - 2023 May 01
Validation Technician, Mid-Level
Hillsboro, OR
... – Manhattan, KS Skills Analog and digital electronic design Building and troubleshooting electrical circuits C, C++, Verilog, ARM Assembly Language, MATLAB, and LT Spice PCB design and layout in Eagle CAD Use of electrical lab equipment such as ... - 2022 May 31
... – Manhattan, KS Skills Analog and digital electronic design Building and troubleshooting electrical circuits C, C++, Verilog, ARM Assembly Language, MATLAB, and LT Spice PCB design and layout in Eagle CAD Use of electrical lab equipment such as ... - 2022 May 31