Chandana Sai Thondebhavi Shanthakumar

ad2kf3@r.postjobfree.com +1-510-***-**** LinkedIn Sacramento, California EDUCATION

Master of Science in Electrical and Electronics Engineering August 2021- December 2023 California State University-Sacramento, California, USA (GPA: 3.5/4.0) Relevant coursework: Analog Mixed-Signal IC Design, Adv Digital Signal Processing, Wireless Communication and network Systems, Adv Computer architecture, Modern Antenna Design, Microwave Engineering, Statistical Theory of communication. Bachelor of Technology in Electronics and Communication Engineering August 2017- July 2021 Gandhi Institute of Technology and Management, Bengaluru, INDIA (GPA: 3.14/4.0) Relevant coursework: Digital Logic Design, Basic VLSI design, Digital Design with Verilog, Microprocessors and interfacing, RF Cellular communications, Optical communications, Satellite communications, Antennas and wave propagation, Linear integrated circuits, Electromagnetic waves, Electrical Circuit Theory and Analysis.

SKILLS

Programming Languages: Python, Java, MATLAB, GNU Octave, Verilog (HDL) Tools: Cadence PSpice, NI LabVIEW, Xilinx Vivado, Ansys HFSS, Modelsim, Cadence Virtuoso, Cisco Packet Tracer, Google Cloud Platform, NI Multisim, Simulink

WORK EXPERIENCE

INTERN Indian Institute of Science – Bengaluru, INDIA June 2022-December 2022

• Efficiency Analysis of Edge and Cloud Computing Models o Conducted a comprehensive comparative analysis to evaluate the efficiency of Edge and Cloud computing network models. o Analyzed factors such as latency,data processing speed,and resource utilization to assess the performance differences between the two models. Gathered and analyzed real-world data to make informed recommendations for specific use cases.

• Real-Time Cloud Architecture Applications

o Designed and implemented real-time Cloud architecture applications to meet the demands of modern data processing and communication needs. Developed applications that leveraged Cloud services for seamless scalability, flexibility, and responsiveness.

• Network Modeling and Simulation

o Utilized Cisco Packet Tracer, a powerful network modeling and simulation tool, to create detailed network models. o Simulated various network scenarios to evaluate performance, security, and scalability. o Leveraged the results of network simulations to make informed decisions and optimize network configurations. Research Assistant California State University-Sacramento August 2022 – December 2022 Created Cross-Layer V2X Security Protocol:

• Covered physical, data link, network, transport, and application layers.

• Implemented strong encryption and authentication for data confidentiality, integrity, and authenticity.

• Enhanced security promotes safer interactions in connected transportation systems, enhancing road safety and reducing cyberattack risk ACADEMIC PROJECTS

Simulation of Edge Computing network models Cisco Packet Tracer Indian Institute of Science, India June 2022-September 2022

• Designed and simulated Edge Computing models for real-time applications, including vermiculture and water clogging, using Cisco Packet Tracer.

• Conducted a comparative analysis by simulating Edge network models and comparing them with Cloud models, resulting in valuable insights

• This project paper was published at an IEEE event called IITCEE in the year 2023 - https://ieeexplore.ieee.org/document/10091014 Building and testing of a Dipole and Patch Antenna CSUS February 2022-March 2022

• Constructed a patch antenna physical model using copper dielectric material and plexiglass substrate. Fabricated a dipole antenna using conducting material. Using the HFSS (High-Frequency Structure Simulator) tool to determine the dimensions of the antennas.

• Conducted dimension analysis at a frequency of 1.8 GHz within an anechoic chamber. Construction and Analysis of Dipole Antenna and Probe Feed Patch Antenna Ansys HFSS CSUS January 2022

• Designed and constructed operational Dipole and Probe Feed Antennas using HFSS software.

• Conducted thorough analysis and testing of antenna performance across various frequencies. Designed, a CMOS Inverter as an amplifier and Operational amplifier Pspice Cadence tool CSUS September 2021

• Designed and tested analog amplifier circuits to ensure their functionality.

• Utilized simulation plots to illustrate results obtained from a distinct CMOS process, facilitating an in-depth understanding of DC, AC, and transient characteristics for analog amplifiers.

• Employed a 0.13μm CMOS process with a supply voltage (VDD) of 1.2V for this project. Synthesis and Simulation of Heterogeneous Adders Xilinx VIVADO GITAM March 2021- September2021

• Focused on simulating heterogeneous adders, emphasizing effective low-power and design techniques.

• Developed an area-efficient chip design to reduce cost and weight, making devices more portable.

• Utilized the VIVADO tool for simulation and design. CERTIFICATIONS

• Introduction to Electronics

• Digital Systems - From Logic Gates to Processors

• The Complete Python 3 Course: Beginner to Advanced

• Networking Foundations: Networking Basics

• FPGA Computing Systems: Background Knowledge and introductory materials

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