Ic Design Engineer

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Richard Lin

*************@*****.*** ● 503-***-**** ● Portland, OR 97229

Executive Summary

IC Designer/Technical Leader with extensive design experience in RF/mmWave/analog mixed signal IC, RF transceiver, RFFE, and AiP. Deep understanding of high-frequency package models, device nonlinearities, and noise's impact on circuit and system performance. Demonstrated leadership in innovative product IP development, planning, and effective communication with system architects, Modem/DSP developers, and digital IC designers

Professional Experience

Founder/CTO/Principal Consultant, 07/2016-Present

Smart Connected MicroTech LLC, Portland, Oregon, USA

Developed low cost SiGe BiCMOS 28GHz LNA/PA/VGA/PS for 5G beamforming IC (BFIC)

Designed 9.6-12GHz fractional N PLL for 5G BFIC, including MATLAB modeling, low phase noise VCO/divider, PFD/charge pump, LDO, PTAT bias, and frequency doubler IC design

Proposed GaN die and BiCMOS BFIC wafer bonding heterogeneous integration for reduced element low cost 5G AiP. Developed FOWLP package and BFIC co-design methodology

Developed 5-7GHz SOI PA/LNA/Switch IC and GaAs HBT power device die for mid to high power RF SiP flexible integration, achieving 30% cost reduction of high linear WiFi6E/7 FEM

Designed low power CMOS power detector. Provided consultation for improving the linearity of 2.4GHz GaAs HBT PA design, FEM integration, EM simulation, and volume production tests

Designed 2.7GHz SOI switch for DivFEM, including SP10T, MIPI controller, NVG, and ESD design

Co-developed WLCSP RX/TX SAW filters for DivFEM and 5G n41 PAMiF with an ODM partner Sr. Staff RF/Mixed Signal IC Designer/Technical Leader, 04/2010-04/2016 Intel Inc., Mobile Communication Group, Hillsboro, Oregon, USA

Designed a 2.6GHz SOI PA for 5G/IOT, achieving a 25% increase in output power while maintaining good linearity, efficiency, and reliability. Proposed an innovative envelope tracker and its RF/MS co-sim model framework for envelope tracking PA efficiency optimization

Led 14nm FinFET CMOS RFDAC-based 5G/IOT cellular polar DTX Transmitter IP development. Coordinated cross-site (OR-Munich-Villach-India) activities for circuit, layout, and package design

Designed 14nm FinFET RF/mmWave test structure, low power WiFi/IOT LNA/Mixer/TIA/VCO IP

Led DTCXO IP advance development, including design of 14bit DCXO, 12bit SAR ADC, TDC, LDO, a digital LUT, and IP integration with a 2x2 WiFi transceiver. The silicon showed excellent results with +/-0.5ppm frequency accuracy across the temperature range of -40 C to +85 C Staff RF/Analog IC Designer /Design Lead, 01/2008-03/2010 Intel Inc., Mobile and Wireless Group, Hillsboro, Oregon, USA

Proposed an innovative CMOS analog mixed signal DTCXO using system-assisted calibration for Intel’s WiFi/BT/GPS products, potentially saving $20M in high-volume shipments

Conducted pre-silicon proof of concept activities, including investigation of clock accuracy impact on GPS baseband engine and DTCXO+PLL system modeling using MATLAB/AMS simulation

Led DTCXO building block prototyping. Designed and taped out 14bit sigma-delta modulated DCXO and temperature sensing 12-bit SAR ADC with first-pass silicon success Sr. RF/Analog IC Designer, 11/2005-11/2007

Intel Inc., Mobile and Wireless Group, Hillsboro, Oregon, USA

Led the design of WiFi/WiMAX PLL, achieving industry leading phase noise performance

Resolved issues of PLL fractional spurs and phase noise of Intel’s high volume 802.11a/b/g/n RF transceiver product. The proposed fix achieved a 5~6dB phase noise improvement

Designed low phase noise Xtal clock/buffer for Intel’s high volume Shirley Peak WiFi products 2

Richard Lin

*************@*****.*** ● 503-***-**** ● Portland, OR 97229 Sr. RF IC Designer, 04/2004-11/2005

Motia Inc., Pasadena, California, USA

Designed 9.6-11.8GHz fractional N PLL for WLAN smart antenna chip products SAC168

Designed 38.25MHz differential crystal oscillator, poly-phase filter, LO buffer/driver, and SSB mixer for IDP100 IF beamforming chip product using TSMC 0.18um CMOS process RF IC Researcher Trainee, 09/1999-12/2000

Motorola Inc., Mesa, Arizona, USA

Proposed and designed 2.4/5.8 GHz low phase noise RF CMOS VCOs using a low frequency feedback technique for 1/f flicker noise up-conversion suppression in SiGe:C BiCMOS process Skills

CAD tools: MATLAB, Verilog/VerilogA, Synopsys Hspice, Cadence tools (Spectre, ADE/Virtuoso XL), Cadence EMX, Agilent ADS/Momentum/FEM, Ansys HFSS, Mentor Graphics Calibre, Helic tools Measurement Equipment: Agilent vector network analyzer, spectrum analyzer, frequency count, power meter, oscilloscope, signal and function generator, noise measurement and load pull system, Cascade microwave probe station

Computer Language and OS: C/ C++, Python, Java, VB, Assembly, Linux/Unix/Window Selected Publications

“RF Noise Characterization of MOS Devices for LNA Design Using a Physical-Based Quasi-3-D Approach”, IEEE Trans Circuits and System II, 2001

“Fully integrated 5GHz CMOS VCOs with on chip low frequency feedback circuit for 1/f induced phase noise suppression”, ESSCIRC, 2002

“A 1x2 MIMO Multi-Band CMOS Transceiver with an Integrated Front-End in 90nm CMOS for 802.11a/g/n WLAN Applications”, ISSCC, 2008

“An in-situ temperature-sensing interface based on a SAR ADC in 45nm LP digital CMOS for the frequency-temperature compensation of crystal oscillators”, ISSCC, 2010 Education

University of Waterloo, Waterloo, Canada

Ph.D. in Electrical and Computer Engineering

University of Waterloo, Waterloo, Canada

MASC in Electrical and Computer Engineering

Southeast University, Nanjing, P. R. C

B. S. E. E. in Electronic Engineering

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