| Resume alert | Resumes 61 - 70 of 118 |
RTL design and verification
New Delhi, DL, India
... Summary Good Understanding of the ASIC and FPGA Design Flow. Extensive experience in writing RTL Models in Verilog HDL with all coding styles and flat and layered Testbenches in System Verilog. Expertise in verification methodologies like UVM, OVM. ... - 2015 Oct 07
... Summary Good Understanding of the ASIC and FPGA Design Flow. Extensive experience in writing RTL Models in Verilog HDL with all coding styles and flat and layered Testbenches in System Verilog. Expertise in verification methodologies like UVM, OVM. ... - 2015 Oct 07
Project Security
New Delhi, DL, India
... Date Period Company September 2014 Till date DKOPLabs Training • Linux • VerilogHDL • System Verilog Description • TCL/TK Project (M-Tec): FPGA Implementation of MD5 algorithm in Password Storage • To analyze the security risks of the hashing ... - 2015 Oct 07
... Date Period Company September 2014 Till date DKOPLabs Training • Linux • VerilogHDL • System Verilog Description • TCL/TK Project (M-Tec): FPGA Implementation of MD5 algorithm in Password Storage • To analyze the security risks of the hashing ... - 2015 Oct 07
Secondary School Training
New Delhi, DL, India
... Implemented gate level circuits on FPGA kits. Programming on data types, data flow modelling and operators. JUN 2014 – JULY 2014 BSNL Summer Training Job Role - Trainee: Overview of - Telecom Network Mobile Network(BTS,BSC,MSC) PCM multiplexing ... - 2015 Oct 04
... Implemented gate level circuits on FPGA kits. Programming on data types, data flow modelling and operators. JUN 2014 – JULY 2014 BSNL Summer Training Job Role - Trainee: Overview of - Telecom Network Mobile Network(BTS,BSC,MSC) PCM multiplexing ... - 2015 Oct 04
Design Engineer Engineering
Greater Noida, UP, India
... school UPBoard PCMB, Hindi English 2005 70.5% TECHNICAL SKILLS HDls : VHDL, Verilog Simulation Tools : Mentor Graphics ModelSim SE6.1a, Questasim Circuit Simulator : Virtuoso (Cadence) Synthesizer Tools : Leonardo Spectrum FPGA Tool : Xilinx ISE 10 ... - 2015 Sep 28
... school UPBoard PCMB, Hindi English 2005 70.5% TECHNICAL SKILLS HDls : VHDL, Verilog Simulation Tools : Mentor Graphics ModelSim SE6.1a, Questasim Circuit Simulator : Virtuoso (Cadence) Synthesizer Tools : Leonardo Spectrum FPGA Tool : Xilinx ISE 10 ... - 2015 Sep 28
Microsoft Office Project
Noida, UP, India
... Tech (EC) 2007 JDSVM, Kanpur 85.17% Class XII (CBSE Board) 2005 JDSVM, Kanpur 78.83% Class X (CBSE Board) Technical Skills C Language, Shell scripting (UNIX) Verilog (Hardware Description Language) AVR Microcontroller, ARM Processor FPGA Spartan 3E ... - 2015 Sep 28
... Tech (EC) 2007 JDSVM, Kanpur 85.17% Class XII (CBSE Board) 2005 JDSVM, Kanpur 78.83% Class X (CBSE Board) Technical Skills C Language, Shell scripting (UNIX) Verilog (Hardware Description Language) AVR Microcontroller, ARM Processor FPGA Spartan 3E ... - 2015 Sep 28
M.TECH VLSI., Trained I.O.T system
New Delhi, DL, India
... • Design and implementation of IC 74138 using FPGA (Xilinx and Mentor graphics). • Integrated Wireless Robotic Intelligence (IWRI) --- On Path Judgment. • Designing of low voltage novel voltage divider biased CMOS Current conveyors. • Designing of ... - 2015 Sep 28
... • Design and implementation of IC 74138 using FPGA (Xilinx and Mentor graphics). • Integrated Wireless Robotic Intelligence (IWRI) --- On Path Judgment. • Designing of low voltage novel voltage divider biased CMOS Current conveyors. • Designing of ... - 2015 Sep 28
Project Training
New Delhi, DL, India
... School RBSE 63.44 2008 Technical Skills: Embedded:- Software Keil, MP lab,AVR studio,Arduino,ISIS Proteus, Xilinx Hardware PCB designing (Bread Board),FPGA,AT89C51,AT MEGA 8/16/32,PIC 16F72/877/874 Software: Assembly language, C language, Matlab, ... - 2015 Sep 27
... School RBSE 63.44 2008 Technical Skills: Embedded:- Software Keil, MP lab,AVR studio,Arduino,ISIS Proteus, Xilinx Hardware PCB designing (Bread Board),FPGA,AT89C51,AT MEGA 8/16/32,PIC 16F72/877/874 Software: Assembly language, C language, Matlab, ... - 2015 Sep 27
Project Design
Noida, UP, India
... SYNOPSIS A VLSI professional with 1 year of experience in design and verification in tevatron technologies Previous 6 months of experience in Networking and security SKILLS Command in verilog/VHDL,system verilog,RTL coding,CMOS,FPGA,ASIC design, ... - 2015 Aug 06
... SYNOPSIS A VLSI professional with 1 year of experience in design and verification in tevatron technologies Previous 6 months of experience in Networking and security SKILLS Command in verilog/VHDL,system verilog,RTL coding,CMOS,FPGA,ASIC design, ... - 2015 Aug 06
Engineering Sec School
New Delhi, DL, India
... Communication System, Digital Electronics PG Title : “FPGA implementation of High Throughput SEFDM System” Description : The future of communication with high speed transmission and effective reception can be incorporated through this technology. ... - 2015 Jul 17
... Communication System, Digital Electronics PG Title : “FPGA implementation of High Throughput SEFDM System” Description : The future of communication with high speed transmission and effective reception can be incorporated through this technology. ... - 2015 Jul 17
vlsi design
Faridabad, HR, India
... School, New delhi 2008 82% TECHNICAL SKILLS Software/Hardware Languages Verilog, Linux, C, VHDL Scripting Languages Bash shell, Awk, TCL/TK Software MATLAB, MS office, MS EXCEL Hardware Designing FPGA Operating System Linux (Ubuntu) and Windows ... - 2015 Jul 16
... School, New delhi 2008 82% TECHNICAL SKILLS Software/Hardware Languages Verilog, Linux, C, VHDL Scripting Languages Bash shell, Awk, TCL/TK Software MATLAB, MS office, MS EXCEL Hardware Designing FPGA Operating System Linux (Ubuntu) and Windows ... - 2015 Jul 16