Jagmeet Singh Hanspal
Systems Software Architect Networks and Timing
firstname.lastname@example.org +91-991******* https://www.linkedin.com/in/hanspal Objective
I have grown grounds-up from developing Software with requirement analysis, design, development, documentation, testing and version-control to having a Design & Architectural-level role & experience in the ASIC/Semiconductor, Embedded and Computer Networking industry. I have a Work/Job-Search SMC (Skilled Migration Category) visa from Immigration Office, New Zealand and I am seeking a Senior Architect/Executive role where I can contribute with my knowledge and experience in Networking/ICT, Embedded Systems and Software. Key Skills and Experience
- Clock Synchronization: IEEE-1588, SyncE (Synchronous Ethernet)
- Applications: MSRP/FQTSS (AVB – Audio Video Bridging)
- Layer-2: Ethernet, VLAN, PPPoE, CHDLC, L2TP
- Layer-3: IPv4, IPSec (ESP, AH)
- QoS: Metering, Shaping, Queuing and WRED
Packet Processing Engine (ASIC) architectures:
- TranSwitch CoPPEn Platform (C programmable)
- Ericsson Spider Programmable ASIC (C programmable)
- Ericsson PPA (Assembly programmable)
- Ezchip ASIC (Microcode)
- Broadcom Trident ASIC
- HPE Rosewood ASIC
Router Architectures I have worked on:
- Juniper T-series
- Ericsson SSR, SE chassis
- HPE Aruba standalone, chassis & VSX
- Ericsson Virtual Router (EVR)
- Open Virtual Switch (OVS)
- Docker, Virtual Box
- AWS Cloud services
Operating System and Programming Languages:
- Regular/Expert: C language, Linux
- Rare: TCL, React, Svelte
- Atmel 8051 with Keil toolchain
- ESP8266 WiFi controller with Arduino IDE
- Raspberry Pi with GCC toolchain
Packet Generators & Analysers: IXIA, Spirent, Wireshark Unit Test Framework: Python based UTF, Tox
Other tools and libraries: GraphViz, Svelte, D3.js, QT (GUI) Electronics: RFID Smart Cards, GPIO, Relays, PIR sensors, 7-segment etc CMS: WordPress and SQL Server hosting on Ubuntu Linux Detailed Employment History
Master Architect May 2018 – Present
Hewlett Packard Enterprise
• Introduced and Architected the AVB (a first for any existing HPE switching product)
• Brought up a team grounds-up and successfully delivered PTP (various HPE-Aruba switching platforms)
• Took over Architect role for Virtual Switching Extension (VSX) team for periodic releases.
• Private VLAN design and feasibility on the Broadcom based switching platform. Key achievements
• 2023: Idea Selection: Method for running PTP BC with VSX
• 2019: HPE Hackathon: Route optimization though time-series traffic prediction model. Senior Technical Lead April 2012 – May 2018
Ericsson India Pvt Ltd
• Implemented Traffic-Steering for IPSEC for particular customer use-cases with NAT and mobile roaming.
• Lead the development and adding support for subscribers over bridge-virtual-instances (BVI).
• Developed L2TP LNS (L2TP Network Server) for the Spider Based 20x10GE cards (Design + Development)
• Added responsibility of acting Agile OPO role to define/manage backlog for L2TP LNS and BVI features.
• Performance scaling KPI in BNG protocols (PPPoE, CHDLC etc) and resolving complex and sticky issues.
• Single-handedly designed Sync-control and RPC related features that improved stability & performance
• Executed Technology-Leadership Project (SDN based Load-balancer) leveraging the Open virtual switch.
• Added PPP/CHDLC protocols for the spider-based POS card with OCn interfaces for SSR router.
• Traveled to Budapest, Hungary for the POS packet-forwarding software during the board bring-up.
• Served as the PoC for Converged Packet Gateway (3GPP CPG) product and resolved several escalations. Key achievements
• 2017: EngiNerd winner for "Smart Conference Rooms with IoT”
• 2016: Cleared Ericsson L1 assessment for management and leadership.
• 2015-16: Ericsson ACE and Rock-star Awards for Quality Focus and Delivery of important projects.
• 2014: Ericsson PDUIP Routers Gold Partnership Award for Quality Focus, Drive and Determination
• 2013: Received “Best Ericsson Innova” award at the Global Ericsson award ceremony in San Jose, California.
• 2012: Ericsson Innova Best Experimentation award for a QT based Application software Senior Software Engineer Oct 2009 – April 2012
• Complete ownership for feasibility, design and development of Synchronous-Ethernet on Terabit routers.
• Provided architectural inputs regarding IEEE-1588 for the T-series routers.
• Diagnostics’ planning for T-series based 4xOC-48 modules.
• Performance testing of 4xOC-48 module with Frame-relay, Cisco HDLC and PPP.
• Implementation of translation-tables in the EZchip Network-processor and device-driver.
• Class-Of-Service Unit-tests using Spirent Router Tester Key achievements
• 2012: Juniper Invention Disclosure for “Achieving time synchronization amongst the line-cards”
• 2010: Juniper Technical Paper contest runner-up for “Clock Synchronization using IEEE-1588” Senior Member Technical Staff Jan 2005 – Oct 2009
TranSwitch Semiconductors India Pvt Ltd
• Complete responsibility of design and development of Ethernet Packet-Processing Fast-Path Firmware
(Classifier, Forwarder, Filter, QoS, trTCM, srTCM, WRED algorithms etc) for TranSwitch’s multi-core parallel- processing system.
• Interfaced with the Systems’ team at the US development center and the Tool-chain team at the Switzerland development Center.
• Development responsibility for clock-synchronization algorithms based on stochastic processes/models. Used Frequency Counter, Time Monitor, CRO and Logic Analyzers for verifying the results under different N/w conditions emulated through IXIA in the lab environment.
• Participated in training on Project Management (PMBoK), Statistics and Microsoft Project.
• Successfully developed coding-conventions for Customizable Multi-core Platform
• Developed a generic Linux device-driver compatible with major TranSwitch’s products.
• Successfully ported the Monta Vista Linux Kernel 3.1 to our TranSwitch Power-PC based evaluation boards.
• MEF compatible device-driver code-generator for standard user experience across devices.
• VLAN module implementation in the device-driver.
• Development of a Demo-Application on VxWorks to demonstrate SONET protection switching. Key achievements
• 2010: Patent: “Packet Processing System On chip device” International Pub. No.: WO/2010/076649
• 2008: Patent: “Method and Apparatus for determining Dynamic Queue Fill Levels”. # 2742/MUM/2008
• 2007: TranSwitch Employee of the Year 1st Runner-up reward. Software Engineer June 2004 – Jan 2005
Freescale Semiconductors (Contractor)
• Modified MetroTRK(an Embedded Debug Agent) to work as a boot loader.
• Worked on correcting Embeddable Flashing algorithms.
• Worked with Metrowerks CodeWarrior Debugger Development team.
• Ported MetroTRK on different Boards with different BSPs.
• TCL scripting to automate XML Register detailing in CodeWarrior 2.1 for ARM. Embedded Systems Engineer May 2003 – June 2004
Alba Control Systems Ltd
• Planned the development of ARM and Linux based Access Control System with IIT-Delhi.
• Re-Engineered the Device-Driver and aided in the Front-end development.
• Programmed other products like Barrier Control, Automated Car Parking in C and Assembly Language.
• Worked in a six-member team for developing a low-cost Access Control System based on Intel MCS-51
• Integrated and deployed projects for Oracle, HCL, Ericsson, Fibcom, Hutch, GE, Indian Airlines etc. Education Qualifications
Post-Graduation (Part-Time) 2008
PG Diploma in IT Management – All India Management Association, New Delhi (India) Bachelors of Engineering (Full-Time) 2002
Electronics and Communications Engineering – CR State College of Engineering, Sonepat (Haryana, India) Community Involvement/Voluntary Work
ESSCI (Electronics Skill Sector Council of India)
SME (Embedded Systems Software) for National Qualification Pack / Standard for the Skill India Initiative. EmTech Foundation (New Delhi, India)
Involved in an advisory role as a founding member for this Embedded Electronics training centre. Personal Interests
Swimming, Basketball, Instrumental Music, Traveling, Adoring the Nature. Personal Attributes
- Analytical as well as Strategic
- Ambitious and Innovative
- High level of Integrity
- Respect for others and nature