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Design Engineer Project

Bengaluru, Karnataka, 560001, India
October 23, 2016

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Mobile No: +91-735**-*****

Permanent Address: #110, Doddarasinakere, Mandya-571422 Career Objective

To contribute my best to the organization by exploring myself through positive approach and team work, improving my technical skills and managing abilities, enhancing professional growth. Profile at a Glance

Currently working as Design Engineer in Cadence Design Systems Bengaluru, from July 2015.

Masters (M.Tech) in VLSI Design & Embedded Systems.

Graduated in B.E, Electronics and communications.

Possessing good knowledge on Verilog HDL, on HVL Languages like System Verilog.

Possessing Good Knowledge on designing digital circuits.

Possessing excellent domain knowledge on Test Chip (TC) RTL design and integration.

Involved in various phases of front end design viz. Analyzing requirement specifications, Architecture closure, RTL coding, RTL Integration, simulation, GLS, LEC, and RTL verification.

Knowledge on APB and JTAG protocols.

Basic knowledge on DFT

Ability to meet tight deadlines

Technical skill set

Hardware Design Languages Verilog HDL, SystemVerilog. Programming/scripting Languages Basics of C Programming, core java, Perl and shell script. Design Tools Used Cadence’s NCsim/ Incisive, IMC, LEC with conformal EC, Spyglass, Stork tool, Virtuoso tools, Spectre circuit simulator, LVS/DRC/QRC tools, and ADE analysis tool, and Modelsim simulator.

Processors & Interfacing Microprocessor (8086), Microcontroller (8051). Packages MS-Office

Academic profile

Qualification Name of the Institution University/Board Year of Passing


(In %)


(VLSI Design &

Embedded Systems)

B.N.M Institute of

Technology, Bengaluru.

Visveswaraya Technological

University (VTU)




(Electronics &


East-West Institute Of

Technology, Bengaluru.

Visveswaraya Technological

University (VTU).



12th std. (II PUC)

Bharathi PU College,


Department Of PU

Education, Karnataka



10th std. (SSLC)

Sri Kalikamba High

School, Mandya.

Karnataka Secondary

Education Examination





‘Diploma in Java Technology’ from NIIT, Bengaluru. Work Experience and projects

Company: Cadence Design Systems, Inc. Bengaluru.

Duration/period: 1 year 3 month (Currently working as Design Engineer) Post: Design Engineer [c] (TC RTL Lead)


1. Test Chip with HDP Tx IP

2. Test Chip with PCIe and USB2 IPs

3. Test Chip with DPhy Tx, DPhy Rx, & USB2 IPs

4. Test Chip with PCIe Gen3 IP (ongoing project)

Contributions/responsibilities in the project:

TC Architecture closure and Documentation

Test chip RTL Design and integration

Responsible for RDF for TC RTL. Responsible for Spyglass Lint, SDC and CDC checks

Complete TC (Test Chip) RTL sanity check using Test Benches. (Team Internal)

TC RTL, GLS and post Silicon debug support

GLS bring up to test the IP(s) Scan chain in the SCAN chip mode using scan shift patterns at TC level (owner for #2 project and complete post silicon debug support)

Responsible for TC RTL TB automation script that generates the test benches for TC RTL.

Other responsibilities includes Synthesis reports review and feedback, LEC rerun and reports review.


Company: Graphene Semiconductor Services Pvt. Ltd, Bengaluru. Duration/period: 10 Months (Agust-2014 to May-2015) Post: Intern Design Engineer

Project: Design of Control Status Register (CSR) for DDR4 memory controller. Academic Projects

1. Design of Control Status Register (CSR) for DDR4 memory controller (M.Tech Project) Company/Institute: Graphene Semiconductor Services Pvt. Ltd. Language of Implementation: Verilog HDL.

Operating system: Windows XP/Vista.

Description: This project deals with the design of Control Status Register (CSR) for DDR4 memory controller. Control register stores different timing parameters to generate different timing delays for various commands for DDR4 memory like refresh, self-refresh, power down entry and exit, read and write operations, On-Die Termination, different modes of operation and also updates the status register when read from or written into registers. The timing parameters are written by the APB Bridge and CSR receives this information through APB slave interface which is at the memory controller side and stores this information in respective registers of CSR. DDR4 core part of memory controller has timing and command generator unit which reads the timing parameters from the CSR and generates timing delays for each memory related commands for DDR4 memory for proper operation and also updates Status Register on each read or writes success/failure.

Paper Publication: Sathish D, Dr. P. A. Vijaya, Mr. Ramudu B, ‘Design and Implementation of CSR for DDR4 Memory Controller’, has been published in International Journal of Electronics Communication and Computer Engineering (IJECCE), Volume 6, Issue 3, pp:335-340, May-2015. 2. Implementation of Music Synthesizer using FPGA (B.E project) Company/Institute: IETE (Institute of Electronics and Telecommunication Engineers), Bengaluru. Language of Implementation: Verilog HDL.

Mini Projects

1. Time precision comparison of digitally controlled delay elements. 2. Implementation of automatic siren using 8051 microcontroller. Achievements and Awards

Received ‘Best outgoing student award BNMIT-2015’ from BNM Institute of technology, Bengaluru.

University 2nd rank holder in 4th semester M.Tech VTU examination.

Recognized with “iDrive-2016” award for ‘automation of the TC (Test Chip) generation platform that automates incremental TC RTL generation, TC RTL TB generation and tfile generation’, from Cadence Design Systems, Inc., Bengaluru.


Quickly Grasp and Learn New Technologies.

Hard working and dedicated towards achieving the objectives and goals.

Self-learning and good team facilitator.

Ability to meet deadlines

Personal Information

Name Sathish D

Date of Birth 06-june-1990

Marital Status Single

Nationality Indian

Known languages Kannada and English

Present address No.31, Bhargavi Nilaya, 1st cross, 1st main, P.N.B Nagar, Near Doctors Colony, Doddakallasandra Post, Bengaluru-560 062. I hereby declare that the information furnished above is true to the best of my knowledge. Date: Yours sincerely

Place: Bengaluru. (Sathish D)

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