Rajani.Inja

Contact: 988*-***-***/acsxsf@r.postjobfree.com

Professional Summary:

Having 3.10 years of total industrial experience.

Worked as a FPGA Design Engineer for a duration of 3.6 years in Accord Software and Systems Pvt. Ltd., Bangalore.

Worked as a Systems Engineer Trainee for a duration of 4 months in Accord Software and Systems Pvt. Ltd., Bangalore.

Experience in developing a design using VHDL,Verilog.

Handle design, development, testing and debugging of the application.

Educational Qualifications & Achievements:

M.Tech in VLSI Design from Guru Gobind Indra Prastha University CDAC, Nodia with 76% in 2012.

B-Tech in Electronics & communication Engineering from MIC of colleage of Technology,AP with 82% in 2010.

INTERMEDIATE from BOARD OF INTERMEDIATE EDUCATION, AP with 96% in 2006.

SSC from SCHOOL OF SECONDARY EDUCATION, AP with 87% in 2004.

Stood as the topper in my branch in academics.

Technical Skills:

EDA Tools : Xilinx Vivado, Xilinx ISE 14.6, Xilinx ISE 12.2, FPGA Editor(Xilinx ISE)

Altera Quartus II, Matlab

Simulation Tools : Xilinx ISim, Modelsim

Debug Tools : Vivado Logic Analyzer and Chipscope

Programming Languages : VHDL, Verilog, C

CPLD/FPGA Micro controllers : Xilinx FPGAs(Spartan 3, Spartan 6, Virtex6, Zynq, Artix 7),

8085 & 8086 Microprocessor, 8051 Micro-Controller

Familiar IP /cores : SDPBRAM, TDPBRAM, DCM, DSP Slice, ROM, FIFO, FFT

Interface/Bus Protocols : UART, SPI, Ethernet, Parallel Bus Interface with Black-Fin Processor

Familiar OS : MS Windows

Work Experience:

Organization : Accord Software Systems Pvt. Ltd., Bangalore Feb 2012 - Till Date

Role : Sr. Systems Engineer [FPGA Design Engineer]

Department : GNSS & Aerospace

Project 1 : Simulator Project

Development Tools : Xilinx ISE 12.2, Vivado 2014.4

Simulation and Debug Tools : Xilinx Isim,Chipscope,Vivado Logic Analyzer

Language : VHDL

Team Size : 5

Customers : Honeywell,BEL,HAL,VSSC

Project Description:

This is a Research and Development (R&D) project at Accord.The satellite status(position,height,health,velocity of motion,time) is taken interms of ephemeris, almanac and horizontal and vertical position parameters are grouped and stored into a memory.These grouped parameters are taken in the messages format(Measurement data message, C/A code message, Navigation message and Carrier Message).Ethernet(10/100 Mbps) interface is used to interface the messages data from GUI(Graphical User Interface) to the processor.This data is taken into Virtex 6 FPGA using EBIU interface.PPS and BPSK modulated signals are generated from FPGA and the BPSK modulated signal is given to the LVDS DAC.This project is done for GPS(14),GLONASS(14),IRNSS(22), SBAS(3) Constellations(53 satellites).

Now the other constellation sstellites like BeiDou, Galileo, QZSS with more number of satellites is in progress in Artix-7 FPGA.

Responsibilities :

Designing the Simulator project.

Implementing the synthesizable RTL code for all the designed modules.

Designing efficient test bench to verify design functionality.

Testing the design functionality by using test bench and then validating the results.

Generating the bit stream with proper user constraint file (ucf file).

Checking the timing analysis (STA) report: setup and hold time check.

Behavioral Simulation.

Validating the design on the hardware.

Project 2 : ATDL(Air Transport Data Link Layer) Transponder Project

Development Tools : Xilinx ISE 12.2

Simulation Tools : Xilinx Isim

Language : VHDL

Team Size : 3

Customer : L3 - ACSS(Aviation Communication and Surveillance Systems)

Project Description:

This is a Verification and Validation (V&V) project.The design to be tested (DUT) is gien by the customer and the requirements to be tested are given.The test cases are developed in to text files interms of pseudo-commands using the requirement document.The test bench is developed in such a way that it reads the test cases written in the text file, decodes the input from the text input, generation of control and data signals according to the required protocol, reading DUT outputs and comparison of data with the expected result.The output of the test results are taken into log file.

Responsibilities :

Designing and Implementing the efficient test benches for the given RTL code.

Integrating all the TB modules.

Writing the top level test bench to verify design functionality requirements.

Validating the design requirements: The top level test bench invoke the sub-test benches by reading the commands written in the script file (text file) then validating all those commands corresponding to the design requirement document.

Project 3 : IRNSS Receiver Project

Development Tools : Xilinx ISE 13.3, Vivado 2014.4

Simulation and Debug Tools : Xilinx Isim,Chipscope,Vivado Logic Analyzer

Language : VHDL

Team Size : 4

Customer : ISTRAC(ISRO Telemetry Tracking and Command Network)

Project Description:

In this project the accurate position and the rate of motion (velocity) and acceleration of the satellite is determined by acquisition and tracking methods. The signal generated through the simulator project is considered as an input to this receiver project. Based on this, position, time, height, angle, velocity of motion of the IRNSS are determined.

Responsibilities :

Designing the IRNSS Receiver project.

Implementing the synthesizable RTL code for all the designed modules.

Designing efficient test bench to verify design functionality.

Testing the design functionality by using test bench and then validating the results.

Generating the bit stream with proper user constraint file (ucf file).

Checking the timing analysis (STA) report: setup and hold time check.

Behavioral Level Simulation.

Validating the design on the hardware.

Project 4 : All In View Receiver (GPS, GLONASS, IRNSS, SBAS, BEI-DOU, GALEILEO, QZSS)

Development Tools : Xilinx 14.6, Vivado 2014.4

Simulation and Debug Tools : Xilinx Isim,Chipscope,Vivado Logic Analyzer

Language : VHDL

Team Size : 4

Project Description:

This a development project at Accord. AIV Receiver is used to find the very accurate position, time, angle, height and motion of velocity of the satellite.

The acquisition and tracking methods are used to find the status of the satellite. These two methods are implemented for all the constellations like GPS, GLONASS, IRNSS, SBAS, BEI-DOU, GALEILEO, QZSS with more number of satellites is implemented in Artix7 and Zynq FPGAs and testing is in progress

Responsibilities :

Designing and Implementing synthesizable RTL code.

Integrating all the RTL modules for acquisition process.

Writing test bench to verify design functionality.

Validating the design on the hardware.

Project 5 : Implementation of Sub-Modules

Development and Simulation Tools : Xilinx ISE 14.6, Xilinx Isim

Language : VHDL

Project Description:

1.Implementing and testing of inference code of IP cores (DSP Slice).

2.Implementation of the functionality of IIR filter.

3.Implementation of initialization and displaying of data in LCD((320*240) – size).

Acadamic Projects:

M. Tech. Project 1:

Project Title : Development of Radix-2 based 1024-point FFT Implementation

Project Description :

The 1024-point FFT (both Decimation in Time (DIT) and Decimation in Frequency (DIF)) is designed and implemented. The Radix-2, Radix-4 and Mixed Radix based FFT is implemented. The efficient test bench is written to test the design functionality and timing requirements.

Platform: Matlab R2010a, VHDL

Development Tool: Xilinx 12.2

Debug and Simulation Tool: Xilinx Isim

Duration: 5 months

Organization: Accord Software Systems Pvt. Ltd, Bangalore.

M. Tech. Project 2:

Project Title : Design and Analysis of Sense Amplifier Based Flip Flop

Project Description:

To minimise the delay between the latest point of data arrival and output transition in Flip-Flops. In order to reduce this delay in Flip-Flops, sense amplifiers are used to design the Flip-Flops. Typical representatives of these structures are Sense amplifier based Flip-Flop(SAFF),Transmission Gate Master-Slave Flip-Flop(TG-MS FF),C2MOS Master Slave Flip-Flop(C2MOS MS FF).

Platform : Tanner EDA, IC Station

Duration : 5 months

Organization : CDAC, Noida.

B. Tech. Project 1:

Project Title: Development of GSM Based Moving Message Display

Project Description:

To design and develop moving message display board with GSM as source for messages. The designed Scrolling Message Electronic Board displays the large amount of information received as SMS in different bright colours. No distance barriers will be there and hence provides full flexibility to the user to operate the display board from anywhere within sections.

Platform: Assembly Language

Duration: 5 months

Organization: MIC Technology, Hyderabad.

Personal Skills:

A pleasant personality with strong analytical, good communication and presentation skills.

Responsible, Reliable and Self-starter.

Respond positively to a challenge with patience and tolerance.

Achievements:

Placed 1st in academics at school and college level and won the best outgoing student award.

Got good Eamcet and Gate score without attending the training programme

Co-Curricular Activities:

Presented a seminar on “Visual Light Communication System”.

Presented a project on “Audio communication using FO cables” at national level project exhibition contest held at MIC College of Technology.

Attended the workshops “Field Programmable Gate Array” and “Programmable SoC” held at IIT Delhi.

Extra Curricular Activities:

Organized event called “National Level Technical Paper Contest in Aagama’08 held at MIC College of technology.

Organized event called “VLSI and Embedded systems quiz” in Technofest’09 held at MIC College of technology.

Volunteered events in cultural fest held at MIC College, JNTU University.

Personal Details:

Father’s name : Obula Reddy.Inja

Date of Birth : 06-07-1989.

Hobbies : Listening to Music, Gardening.

Address : D/O.I.Obula Reddy, Sri Sai Ladies PG, 330/3,3rd Main,7th Cross, Domlur Layout, Bangalore-560071.

Languages Known:English, Hindi, Telugu and Kannada

Declaration:

I hereby declare that the above written particulars are true to the best of my knowledge and belief.

Date:- (RAJANI.I)

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