Design Signal Processing
Resume:
V ellore Institute of Technology
Kurellagudem, Bhimadole Mandal, West Godavari district, Andhara Pradesh, Pin-534401
MobileNo: +91-955*******, +91-991*******. E-Mail : *******.***@*****.***
O BJECTIVE:
To Purse a career with utilizes my intellectual and analytical abilities and provide me an opportunity to grow and
improve my knowledge in the field of Electronics.
E DUCATION :
Program Institution Year of completion
%/CGPA
M Tech in VLSI Design Vellore Institute of Technology, Chennai 2014
7.78
B Tech in Electronics
GMR Institute of Technology, Rajam 58.87 2009
and Communication Engg
Diploma in Electronics
Sir C R Reddy Polytechnic, Eluru 64.96 2005
and Communication Engg
X Sri Helapuri School 65.83 2002
S CHOLASTIC ACHIEVEME NTS
Qualified three times in Graduate Aptitude Test in Engineering in the years of 2011, 2012, 2014 with
percentile of around 95.
456 rank in the VIT Master’s Entrance examination in the year of 2012.
176 rank in the Engineering Common Entrance Test (E CET-2006).
C OURSE WORK
Analog Electronic Circuits Analog IC Design
Semi conductor Device Modelling Cad for VLSI
Digital IC Design ASIC Design
Digital signal Processing FPGA Based Design
VLSI Testing and Verification System On Chip
Low Power IC Design
Scripting Languages
L ABS
Advanced VLSI Design Lab FPGA Lab
SKILL S
Operating System: Linux, Windows
Programming Languages: C, Shell Scripting, PERL
HDL: Verilog.
Simulator: ModelSim, NC Launch, Cadence Spectre, LT Spice.
Scientific Application: Mat Lab, Keil µ4.
Synthesis Tools used: Xilinx ISE, Cadence RTL Complier
P ROJECTS
M.Tech.: Design of Low Power Analog Active Filters
(Duration 6 m)
Guide: Prof S.Uma Devi, Dept of Electronics and Communication Engg, Chennai.
Designing the Anti Aliasing Filter and Deign of the Data Acquisition System.
Course Projects:
Analog IC Design :
Design of Fully Differential Two Stage Operational Amplifier Using 180nm T echnology Cadence
Spectre Simulator
Low Power IC Design:
Design of SRAM [6T] cell with Low Power consumption using MCML Technique
FPGA Based Design:
Design of Low Power Multiplier using Shift and add Architecture and Implemented using Spartan 3e
FPGA kit.
B.Tech : Pulse compression sequences using the modified simulated annealing algorithm
The algorithm is used for the generation of the good autocorrelation and cross correlation signals,
and those are used signals are used for reducing the side lobes in the Pulse compression techniques,
these techniques are used for the increase the range resolution of the radar.
P ROFESSIONAL EXPERIE NCE
I worked as a Management information system administrator in the PCEPL in Rajasthan.
(Duration 2Y 4M)
P OSITIONS OF R ESPONSIBIL ITY
Teaching Assistant for the Basic Electrical and Electronics circuit course.
E XTRA - CUR RICULAR ACTIVITIES
Participated in Intra college cricket competition in the Engineering College.
Participated in National Instruments educator day 2012.
Participated in Blood Donation camp conducted by Indian Red Cross Society.
A REA OF INTERESTS
Signal Processing
Digital Integrated Circuits
Analog Integrated Circuits
DECLARATION
I here declare that the above mentioned all information is true to the best of knowledge and If you
found any false information given b y me you can tentatively reject me at any mode of recruitment process
.
Place: Chennai VASANTHAROY ANNAMREDDY
Date : 04-04-2014
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