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System Engineer/Hardware Design Engineer

Location:
Colorado Springs, Colorado, United States
Salary:
135000
Posted:
July 16, 2019

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Resume:

Michael L. Cattolica

System/Hardware Engineer

Updated 01 Mar 2019

EXPERIENCE SUMMARY

Chief/Principal System/Hardware/Firmware Design Engineer Digital Signal Processing/Control Electronics hardware and firmware design engineer with more than twenty five years of experience in all aspects of engineering disciplines, from concept to installation and support. Designs in avionics, radars, sensors, missile systems, satellite systems and digital signal processing. This experience includes design, test and integration, testing and product evaluation, team management and project/program.

Specified, architected and designed DSP boards based on VME, PCI, PMC and cPCI buses. Designed DSP applications in C/C++ and MatLab. Designed digital receiver components for radars and signal intelligence systems based on COTS and custom products. Developed systems based on DSP vector processors, re-configurable compute elements (FPGAs and CLPDs) and general-purpose processors for very high bandwidth applications.

EDUCATION / SPECIALIZED TRAINING

B.S. Electronic Engineering, California State University, Long Beach, California, 1981

B.S. Ocean Engineering (minor study), California State University, Long Beach, California, 1981

ITT- Green Belt Training, Robust Engineering, MatLab and MBSE SysML certified.

CHRONOLOGICAL WORK EXPERIENCE

May, 2006 – Present

Harris Corp., Space Superiority – Space and Intelligence

Exelis Inc., Information Systems Division

ITT Industries, Systems Division, MS-SENSOR

SENSOR Program – Colorado Springs, CO

Project Engineer Project Engineer for the Eglin and PARCS Radar Weapon Systems. Responsible for leading projects to monitor/maintain cost and schedule performance. Review engineering designs for technical

Chief System Engineer Chief System Engineer for the BMEWS/Pave PAWS Weapon System. Responsible for the overall system design and maintenance. Developed the top level System Requirement Document (SRD). Lead Mobile Depot Maintenance teams for repair of the systems.

Principal Electronic/Digital Engineer Hardware/Firmware Engineer for the Eglin Weapon System. Tiger Team Member responsible for completing/deploying/delivering the Control and Signal Processor Upgrade (CSPU). Responsible for evaluation/redevelopment of the FPGA firmware.

Principal Electronic/Digital Engineer System/Hardware/Firmware Engineer for the PARCS Product line. Responsible for development of FPGA firmware, simulation environments, and interfaces for deployment of redesigned sub-systems into an existing radar system. Determine the system design tradeoffs using analysis techniques to partition functionality between software and hardware. Working knowledge of the system working parameters for hardware/software compatibility. Develop the system interface control documentation for integration of new equipment with legacy equipment. Responsible for the system, analog, digital and FPGA design.

Jan, 2004 – May, 2006

ITT Industries, Systems Division, CIS – Colorado Springs, CO

Senior System Engineer Senior Engineering Specialist/Systems Engineer for the Satellite Communications projects-IMPCS, GSCCE and RSCCE. Responsible for system hardware design and configuration. Supported integration and testing between system concepts and vendors delivered hardware. Supported projects during customer requested Engineering Change Proposals. System Engineer supporting the GPS-NRS subsystem, developing operational software and circuit firmware.

Oct, 2000 – Oct, 2003

Real Time Logic, Inc. – Colorado Springs, CO

System Engineer Product manager for the Telemetrix 70/70 (T70/70) systems. The T70/70 is a fully integrated hardware and software suite that provides ground antenna site telemetry/command IF and baseband signal processing functions for SGLS or non-SGLS requirements. Responsible for integration of the T70/70 units and racks for customer projects.

Designed a high rate Frame Synchronizer for use in CCSDS applications. The Digital CCSDS Processor utilized an ASIC Viterbi Decoder and Reed-Solomon FEC Decoder. The Frame Sync allows users to capture block and non-block data for post processing of the Satellite Telemetry.

Jan, 1996–Sep, 2000

Catalina Research, Inc. – Colorado Springs, CO

Staff Engineer Manager of the Application Engineering group. Responsible for hardware/software product integration for customer applications. Aid in all aspects of customer support from the system conceptualization to application development. Coded DSP applications in C/C++, MatLab, and VxWorks. Developed reconfigurable compute elements using VHDL and Xilinx FPGA tools. Wrote technical proposals and white papers describing the practical applications of CRi DSP products.

Designed the Digital Receiver (DiRec) board for pre/post-processing of the radar data applications. The DiRec contained FPGAs for implementing customer specific applications. The DiRec utilized ASIC digital mixers and filters for processing.

July, 1976–Jan, 1996

Previous Employment Summary

Engineer Over twenty years of experience designing electronic equipment from boards to systems. Worked for more than twelve years as a self-employed contract engineer. Experience performing engineering responsibilities for government contractors such as Hughes Aircraft, Rockwell International, Interstate Electronics, NASA/Jet Propulsion Laboratory as well as commercial companies including Hewlett-Packard, Quantum and Mekel Engineering.



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