Product Design and Development Engineering. Design new Products, maintain current products, sustaining engineering of legacy products.
Dzyne Technologies Contract (Military) OCt./2018 - Dec,/2018
Designing PCB. BLDC Motor controller, Embedded processor (SoC). Firmware design Altium designer
Developed Embedded firmware for the control system. Military applications.
Designed motor controller using Cypress, PIC32 and Battery power distribution to power and control brushless DC motors to fly the drone. Power in excess of 30KW and MOSFET motor drivers and controllers (SiC)
Schematic and PCB design using Altium (18.1). Flight computer using NXP and Serial communication to the
motor controller for flight control.
Developed test and quality plans to pass DoD requirements and ready for manufacturing and obtaining first article for successful flight test
Interface to camera for aerial view of the terrain to monitor proper flight and mission fulfillment.
Marvin Test Contract (Military) June/2018 - Oct/2018
Design FPGA based hardware design. Develop Verilog and VHDL firmware code Altium designer
Developed all firmware for the hardware for Military applications
Western Digital August/2011 – June/2018
Sr. Principal Staff Engineer
Working in the product design group to develop next generation Solid-State Drive technology with 24nm and
19nm NAND flash (cMLC and eMLC) for SATA, SAS and PCIe SSD products.
Perform signal integrity, power integrity, PCB layout, High speed DDR3, SerDes and ASIC for the PCIe, SAS
and SATA SSD drives and design of new products and obtaining FCC certifications.
I have setup PCIe, SATA, and SAS compliance test stations to perform in house first pass compliance tests
for PCIe Gen3 including NVME,, SATA, SATAe and SAS products.
Designing 12G SAS Gen5 using IBM Core. In charge of PCIe Gen3 with NVME design.
Implemented a rapid development graphical VHDL workflow. Workflow includes Clearcase, HDL
Designer, Synplify Pro and LutM fpga technology. Robust FPGA server peripherals include DDR1, DDR2,
Very High Speed serdes resources.
Translated game changing algorithms into fpga firmware for real time implementation.
Provided consultation to mitigate printed wire board μV EMI problems with proper return current
layout.Completed RTL Code Development in VHDL, and Validation of the design for a Video Display section.
Integrated a Model of the IDT Dual Port Sram in the Test Bench - design was synthesized for a Vertex II
InTheAirNet – Irvine, CA 5/2007-August/2011
Systems Test and Integration Lab Manager/Director of Design And Development Engineering
Designed 30000 gate 22nm mix signal ASIC to minimize design component counts and minimize cost.
Designed Active Array and Electronic Steering algorithm to operate from 9.5 to 12.75 GHz in both Linear and Circular Polarized Satellite systems. The mean gain of the antenna is about 8.4 dB with a G/t of 9 dB/k over the entire band (DVB-T/TH). Designed with RoHs qualified components. telemetry formats (CCSDS, TDRSS)
Designed SerDes (TX Equalization, De-emphasis, RX, AGC, CDR, PLL, VCO) RTL building block.
Designed multiple microprocessor based boards and designed and developed BIOS and developed testing.
Designed touch screen LCD with LED back lighting capability using captive sense technology.
Designed 803.2u 100Based, 10Based and 100Base-T switching and routing products.
In charge of setup and running EMI/EMC (DO-160, MIL-STD 810/820 E3, D0-254, FAR15, MIL-STD-1472) QTP and ATP
Tested Analog Device Blackfin BRAVO for voice and video over IP by designing reference hardware and software by configuration two LRU's in two different physical locations. Used for IFE system.
Developing MPEG-2/4 video/audio stream over GigaBit Ethernet using Davinci DSP and Xilinx (MicroBlaze) FPGA with ARM7 processor including Freescale. Used WireShark extensively for network analysis, fault discovery, fault isolation, and fault injection. Automation using NI LabView software.
Performed component engineering; RoHs, WEE, Conformity, availability, lead time, end of life, life time but out, component substitution, defect analysis. Automating testing using LXI, Agilent IO, LabView.
Designed mezzanine PCIe 2.1 host PCBA using micro strip design for impedance matching and bus speed up to 2000MHZ for use with DDR5 Memory Devices. All designs are based on DO-254.
Designed 802.11n wireless connectivity for ease of operation designed using Motorola Android processor (Motorola CLIQ™ with MOTOBLUR™) under Android v2.1 RTOS for low power applications using most popular apps. CDMA 1xEV-DO 800 / 1900 was deployed. 802.11n used for remote access.
Designed radio based R.F. product based on Ericsson OSS (LTE, UMTS, GSM) including CNAI, Performance RAN Measurements (GPEH, UETR, etc.), AMOS
Thales Avionics – Irvine, CA 11/2005 – 5/2007
Principal Electrical Engineer/Sr. Principal Systems Enginneer-IPTLead
Sr. Principal Staff Systems Lead Engineer
Designed automated test fixture for DVT, ATP and QTP.
Designed dual PowerPC processor board and design, developed the BIOS.
Designed product deploying with PowerPC and Xilinx and Altera FPGA’s. All designs are based on DO-254.
In charge of setup and running EMI/EMC and ESS/HASS and HALT.
Used WireShark extensively for network analysis, fault discovery, fault isolation, and fault injection.
Raytheon Corporation – El Segundo, CA 7/2003 – 11/2005
Sr. Principal Multi Discipline Engineer (Software and R.F.)
Lead system integration engineer for Air Force UAV imaging system (SAR and EO/IR). With FAA guidelines for development and certification of electronics and software such as DO-254,FAR, RTCA-178B, ARP 4754, MIL-STD-1760, MIL-STD-1970; MIL-STD-1553, DO-160.
Designed (ALTERA and XILINX based image processing operating at 2GHz and data width of 64 bit using ATPG generation/validation. This is a $25 Million AeroSpace Military product.
Designed hardware and software using Ethernet, CAN, 1555B and ARINC bus.
Designed Synthetic Aperture Radar Antenna sub system and wave guides.
In charge of system testing for the Wireless Lan based on the 802.11(a, b, g and n) and Motorola based CDMA. WIRELESS TELECOM/SOFTWARE ENGINEER/PROTOCOL TESTING CDMA/iDEN PROFILE and CDMA-Protocol testing for field (soldiers, field operation, and base command). Extensive use of WireShark.
Frontier Systems, Inc. – Irvine, CA 1/2002– 7/2003
Chief Lead Systems Engineer (Government/Military)
In charge of development and design of test plans and automated test stations and execution of the plans to completion.
Designed avionics chassis and back plane to accommodate flight computer and control systems, radio communications and power supply.
WindRiver Systems – Irvine, CA. 5/2001 – 12/2002
Lead Systems Test Engineer/Systems Engineer
In charge of development and execution of test plans and procedures for OSPF and 802.11a/b/g/n routing Protocols (RFC1583, RFC1278, RFC2328, RFC1850, and SNMP), Fiber Channel, EO/FC, and Infiniband.
Developed test scripts (TCL and C and Perl under Solaris) for IXIA test equipment and ANVL in order to automate the test efforts. Used WebLogic, Winrunner, Rational Robot, and Rational Test Manager, ClearQuest and Segue SilkTestfor further GUI and other testing. Extensive use of WireShark for network and protocol analysis.
Designed and developed BIOS for different microprocessor boards (XScale, ARM, i960, RISC, Itanium, etc.)
Gadzoox Networks – Irvine, CA. 12/1998 – 5/2001
Sr. Principal Design Verification Engineer
Responsible for development and execution of test plans and procedures for Fiber Channel switches. including procurement and set up of a very large Fibre Channel test lab, and ASIC verification using Xilinx FPGA, Verilog, and VHDL.
Used WebLogic, Winrunner, Rational Robot, Rational Test Manager, ClearQuest and Segue SilkTest for further GUI and other testing and testing of Fiber Channel Switching Fabric products.
In charge of setup for UNH/IOL interoperability and SanMark test scripts generation and completion of tests.
Received employee of the year and presidential recognition awards.
Rockwell International Newport Beach, CA 11/1996 – 12/1998
Sr. Systems Engineer/Device (ASIC) Design, Verification Test Engineer
In charge of development of test plans and procedure for High speed FastEtehrnet for single and multiple MAC/PHY devices, including 8 port Switch. ASIC Verification is performed by utilizing Agilent 93K.
Responsible for development and implementation of test plans and test procedures for high- speed Ethernet LAN devices. These devices are the PCI, MAC and Physical interfaces for 100BASE-TX/T2 and 1000MBPS IEEE802.3z. ASIC Verification by utilizing Agilent 93K.
In charge of design and testing of Dead Reckoning and Differential GPS ASICs for militray.
Retix Corporation – Santa Monica, CA 5/1993 – 11/1996
Sr. Systems Quality Assurance Engineer/Sr. Systems Engineer
Trained other SQA engineers for understanding IP, IPX, RIP, OSPF, DECNET, AppleTalk, Frame Relay, ISDN and LAN Bridges and Routers.
Configured a large NetWork, which includes several Novell file servers, SUN workstations, OS/2, and Windows NT client/servers for testing the Bridge/Router products. The LAN consists of ATM, FDDI Ring, Token-Ring, and EtherNet. The WAN includes V.35, X.25, ISDN, Switched 56K lines and switched PBX.
MetraByte Corporation – Taunton, MA. 6/1988 – 5/1993
Senior Technical Support Engineer/Software Support Engineer
In charge of providing pre-sales and post-sales assistance to customers for using Data acquisition products, Machine Vision (Frame Grabber) and GPIB hardware and software
Responsible for providing customers with sample programs written in C, Fortran, Pascal, and Basic for products, which include Language Interface Libraries.
Concord Data Systems – Concord, MA 4/1986 – 6/1988
Senior Test Engineer
Responsible for design, development and implementation of telephone line simulator based on the 8051 micro-controller and TMS32020 D.S.P. utilized to test high-speed modems (9600 BPS).
Designed test equipment to test high-speed modems, including SFI, TONE, WHITE NOISE, IMPULSIVE NOISE, GAIN HITS, RANDOM NOISE, AMPLITUDE JITTERS, FREQUENCY-SHIFT, INFORMATION DISTORTION, GAIN SLOPE, DELAYED SLOPE and DATA COMPRESSION.
Electronics Corporation of America – Waltham, MA. 5/1983 - 4/1986
Designed 8051 microprocessor based industrial programmable controller to monitor and control temperature, pressure, proximity, humidity, vibration and flow. Also developed on board diagnostics.
Designed switching power supply to generate +5VDC, +/-12VDC by incorporating MOSFET's. Also generating an automatic "Power Supply Shut Down Signal" to warn the processor to store the most up to date data and configuration into the EEPROM.
MSEE Electrical Engineering/Computer Engineering
Northeastern University, Boston, MA. 1988 GPA 4.0
BSEE Engineering Science and Engineering/Electronics Engineering
NorthEastern University, Boston, MA. 1984 GPA 4.0
Development Tools: Microsoft Visual Studio, VHDL, Verilog, CEVA SDK, MontiVision, WindRiver BSD SDK, Visual IDE, Cypress, AMD, Intel, Motorola Android, Spansion, Texas Instruments (DSP), Broadcom, Nios II,UnixWare/OpenServer Hardware Developers Kit (HDK.), IN CIRCUIT EMULATOR, JTAG, Fly-By-Wire, sniffer and WireShark. Allegro, Cadence Schematic Capture, Mentor Graphics, Agilent Design Studio, Altium, Eagle
CAD Tools: Orcad, Mentor Graphics, AutoCad 2011, SolidWorks, ProE, PADs, Gerber, Microsoft Visio, MCAD, MATLAB, MATHCAD, CADAM-CATIA V5, PSpice, PCB Tools (PCB-Layout; Simulation; Schematic Capture; Autoplacer; Autorouter; EMC Analysis).
Operating Systems: Windows, OS2, MAC OS, VMware, VMX, Linux, Solaris, Unix, CP/M, DOS, Google Chrome, iRMX, ISIS II, MVS, LynxOS, VxWorks, MonaOS, CISCO IOS, SymBian, Openmoko Linux, AIX.
Hardware: 8080, 8085, 80286, 80C186, 80386, 80486, 68020, 8051, 6800, Pentium and Itanuim family, SCSI,DSP56000, TMS32020, VAX/780, IBMRS6000, MicroVAX/VAXII, HP9000,IBM PC/AT 386/486, IN CIRCUIT EMULATOR IEEE488 GBIP Interface, Agilent 93K, PCI/PCI-X, JTAG, ARM7, Android and Freescale
Programming Languages: C, C++, C# (.NET), Fortran, Visual C, Visual Basic, Java, HTML, LISA, ADA, Pascal, Turbo Pascal, Turbo C/C++, Assembler, Delphi, XML, PhP, Python, Perl, TcL, Mercury Computer Systems, Oracle, Novell, LISP, AJAX, Godiva.
Software Application Tools: Microsoft Office (Word, Excel, Power Point, Visio, Project, Outlook, MS-Synch, Groove, Silverlight), Lotus Notes. Citrix (CPS 4.5, XenApp 5/6) Exchange 2007/2010 Enterprise Storage Management: EMC SAN/ HP MSA/ iSCSI, SQL 2005/2008 SharePoint 2007 Administration Windows Server 2003/2008 Linux: Red Hat/Fedora HP Hardware, MCP/ MCSE/ CCA certification, DNS, LDAP, Active Directory, Veracode, Fortify, Imperva, and Vontu DLP (data linkage protection), PMP lifecycle and PMBOK framework, MS SQL Server, QTP, WebLogic, Winrunner, Rational Robot, Rational, Test Manager, Segue SilkTest and ClearQuest.
Certification and Compliance Agencies: FAA, UL, CE, TUV, CSA, EMC, EMI, DO160, D0254, CISPR, IEEE, MIL-STD. HALT, HASS, ESS.
Protocols: 802.3, Ethernet, 10BASE-T, 100BASE-TX/T2, V.32, V.35, V.24, V.25, SNMP, V.34, V.40, V.42Bis, V.80, RS232, X.24, X.25, IPV6, TCP/IP, Token Ring, DecNet, MNP4, MNP5, T1, CAN, IPX/SPX (NETX), OSPF, DCOM, MPLS, RIP I and II, SNA, Fibre Channel, NetBios, NetBeui, AppleTalk, IBM DOS LAN, NOVELL, ATM (OC3), 802.3u/x GigaBit Ethernet, iSCSI, Ethernet over FC, USB 3.0 and SATA. Voice and video over IP
Certified Netware Engineer, CNE, ECNE, CNI, CAN and MSCE.
I hold Cisco ASA, CCIE, CCISP and CCISP. A+.CISCO Catalyst 7000
SSO (Single Sign On) PMP certified
Member of IEEE EMI/EMC author of training material on EMI/EMC
I have been granted two U.S. Patents and others pending.
ISO9001 and AS900 Certified. Six Sigma Black Belt Master Certified, CMMI Level 5
FAA DER Certified 14 CFR § 183.29 (System and Equipment Engineering)
I have over 20 years of experience with various types of aircrafts. I have been doing installation, maintenance, QC inspection, repair and upgrades.
Eligible to obtain Top Security clearance (TS/SCI/SSBI with Poly).
Managed over 40 engineers.