972-***-**** https://www.linkedin.com/in/badmavathyr email@example.com
ASIC DESIGN, VLSI DESIGN, FUNCTIONAL VERIFICATION AND VALIDATION, RTL DESIGN, HARDWARE DESIGN, COMPUTER ARCHITECTURE
- Innovative and Detail-oriented Electrical Engineer (Digital Systems) actively seeking for Full Time Opportunities immediately.
Master of Science in Electrical Engineering in Digital Systems stream The University of Texas at Dallas, USA 3.275/4.0 Dec 2017
Relevant Coursework: Testing and Testable Design Microprocessor Systems, ASIC Design, VLSI Design, Computer Architecture
Bachelor of Engineering in Electronics and Communication Engineering 8.86/10.0 Apr 2014
University Rank Holder and College Topper from Anna University, Chennai, Tamil Nadu, India
Assistant Systems Engineer TCS Limited March 2015 – July 2015
Exposed to overall SDLC, MVC architecture and trained on Unix/C++ and Oracle 11g Database along with Shell Scripting.
Possess knowledge with hands on experience on Unix, C++, SQL. Developed and implemented workflow automation for the workers in a restaurant using PL/SQL triggers with C++ backend under Unix Environment with CVS check out.
Received ILP Kudos and TCS Gems (Certificate of Appreciation) for consistent high performance.
Languages Verilog, C, C++, Unix shell scripts, VHDL, System C, System Verilog, Python
Assembly Languages 8085,8086, 8051, TI MSP430, ARM Cortex M3
Software Xilinx ISE, MATLAB, Synopsys - Design Vision, Tetramax, Cadence: Virtuoso, Assura, Composer Schematic, HSpice, UVM, Model-Sim, Synopsys IC Compiler, Code Composer Studio, IAR Compiler, Particle IDE
Certifications System Verilog Assertions and Coverage, OVM and UVM test benches from scratch
Trivium Cipher Implementation VLSI Design
Developed Trivium Cipher with Shift registers connected in MATRIX fashion. Design is initially synthesized using Composer Schematic in 130nm CMOS technology. Shift registers are D flip flop with asynchronous reset input and True Single Phase Clock type. Layout was designed using Cadence Virtuoso with Manual Place and Route and Floor-planning, Netlist is generated from the design. HSpice code is written for obtaining the optimum parameters of the design. Achieved minimized area design and obtained ideal aspect ratio. Presentation Link: https://youtu.be/Ux8SO7g9T4U
Design of 1K bit, 6T-SRAM using IBM 130nm Technology AVLSI Design
Designed and Implemented a full chip with Row/Column decoders, write buffer and sense amplifier, with high read stability & static voltage noise margin of 0.58V and write trip voltage of 0.64V using Cadence Virtuoso and Schematic. Leakage reduction by negative gate voltage supply to NMOS write access transistors with leakage power of 27.9nW, read delay of 230ps, read power of 8.12uW, write delay of 106.2ps and write power of 8.78uW.
A Low Power Mini Stereo Digital Audio Processor (MSDAP) design ASIC Design
Designed a application specified chip to implement Finite Impulse Response (FIR) filter which can perform Audio Processing applications. Behavioral code in Verilog and C code is used for functional verification of the design. Synthesis performed using Synopsys Design Vision. Layout generation, Floor-Planning, Place and Route, Timing and Power Analysis were performed using Synopsys IC Compiler and is used for obtaining Optimum Parameters for the design using Tcl Scripting. 93.7% of Floor Plan Utilization Ratio is achieved through the design with no setup and hold violation.
Test Pattern Generation for ISCAs89 S27 Benchmark circuit Testing and Testable Design
Modelled the given benchmark circuit using Verilog HDL description and simulated using Xilinx ISE. Using scan DFT technology, replaced normal flip-flops with scan flip-flops in Synopsys Design Vision to generate netlist. Fault Coverage and Analysis was computed using Tetramax and generated different patters using ATPG.
Multiplier Design – Testing and Analysis Testing and Testable Design
Implemented 4-bit unsigned multiplier using Verilog code and synthesized using Xilinx ISE. 8-bit External-XOR LFSR by making the circuit BIST (Built-In Self-Test) testable as pseudo random pattern generator and 8-bit MISR (Multiple Input Signature Register) as signature compactor. Design is tested for various parameters such as Fault-Coverage, Area and Time analysis with and without BIST for different Fault patterns in Tetramax. Obtained Maximum Fault Coverage by detecting all possible faults.
Cache Design and Branch Predictor – Analysis Computer Architecture
Designed and developed Branch predictor and Cache for Alpha Microprocessor for the given benchmarks: ANAGRAM, CC1 and GO using Simple Scalar 3.0. The design is simulated for various parameters such as various levels, types, different RAS (Return Address Stack) size and Branch Target Buffer with different configurations. Achieved optimized parameters for the design using Data Analysis.
Volunteered in a charity fund raiser event and helped in raising funds of more than 10k USD for the children as part of OVBI.
Coordinated Engineering Week event as a volunteer in Electrical Engineering Stream for multiple events and recreational activities.
Served as a volunteer in Welcome Week event, to invite the International students on-campus by providing warmth and support.