| Distance: | Resume alert | Resumes 31 - 40 of 727 |
Mnc Project
Vasant Nagar, Karnataka, India
... Programming Languages C, C++, Python, Shell Scripting HDL /HVL Languages Verilog Mathematical Tools MATLAB Assembly Programming P8085, C8051, ARM, Rasberry PI EDA Tools Cadence (nclaunch, imc, virtuoso), Keil, LT spice, Xil- inx Vivado Hardware ... - 2021 May 13
... Programming Languages C, C++, Python, Shell Scripting HDL /HVL Languages Verilog Mathematical Tools MATLAB Assembly Programming P8085, C8051, ARM, Rasberry PI EDA Tools Cadence (nclaunch, imc, virtuoso), Keil, LT spice, Xil- inx Vivado Hardware ... - 2021 May 13
RTL engineer
JP Nagar Phase 5, Karnataka, India
... Veoneer india pvt ltd Internship Internship on restraint control systems which deals with the airbag deployment system Maven silicon VLSI design Good skill in advanced digital design, verilog, STA, RTL design, simulation and synthesis. EDA Tools : ... - 2021 Apr 28
... Veoneer india pvt ltd Internship Internship on restraint control systems which deals with the airbag deployment system Maven silicon VLSI design Good skill in advanced digital design, verilog, STA, RTL design, simulation and synthesis. EDA Tools : ... - 2021 Apr 28
Electronics Engineer
Bangalore, Karnataka, India
... and Microcontrollers, Verilog. • MS Office, MATLAB, CC Studio, Kiel, Photoshop, Premier Pro, Cadence(Basics) Painting Drawing Multimedia Editing Meme Making Story writing Writing Presentation Reading novels Attend seminars Debugging Circuits ... - 2021 Apr 22
... and Microcontrollers, Verilog. • MS Office, MATLAB, CC Studio, Kiel, Photoshop, Premier Pro, Cadence(Basics) Painting Drawing Multimedia Editing Meme Making Story writing Writing Presentation Reading novels Attend seminars Debugging Circuits ... - 2021 Apr 22
Information C
Vasant Nagar, Karnataka, India
... U.C NATIONAL PRE-UNIVERSITY COLLEGE DEPARTMENT OF PRE−UNIVESITY EDUCATION 2017 85.5 % SSLC ST.JOSEPH’s PRIMARY and HIGH SCHOOL KARNATAKA SECONDARY EDUCATION EXAMINATION BOARD 2015 87.04% Programming Languages: C,VERILOG HDL Good oral communication. ... - 2021 Mar 21
... U.C NATIONAL PRE-UNIVERSITY COLLEGE DEPARTMENT OF PRE−UNIVESITY EDUCATION 2017 85.5 % SSLC ST.JOSEPH’s PRIMARY and HIGH SCHOOL KARNATAKA SECONDARY EDUCATION EXAMINATION BOARD 2015 87.04% Programming Languages: C,VERILOG HDL Good oral communication. ... - 2021 Mar 21
C, C++, basic Python, embedded C, Linux internals, TCP/IP, UART, I2C
Vasant Nagar, Karnataka, India
... • VLSI design using Verilog. • PLC Automation. • Two weeks course on PCB Designing. • Winner in volleyball intercollege match 2015-2016. • Runner up in basketball intercollege match 2018-2019. • DOB :- 17th Aug. 1997. • Marital Status : Unmarried. • ... - 2021 Mar 15
... • VLSI design using Verilog. • PLC Automation. • Two weeks course on PCB Designing. • Winner in volleyball intercollege match 2015-2016. • Runner up in basketball intercollege match 2018-2019. • DOB :- 17th Aug. 1997. • Marital Status : Unmarried. • ... - 2021 Mar 15
Engineer Engineering
Bangalore, Karnataka, India
... Mathlab, Xilinx, Turbo C++, Verilog Career Summary IT Support Engineer Workshops Image Annotation, Data Annotation, Media annotation, AI annotation Checks feasibility of software prototypes Modifies code to fix errors Mansys Infotech Pvt Ltd. VLSI ... - 2021 Feb 24
... Mathlab, Xilinx, Turbo C++, Verilog Career Summary IT Support Engineer Workshops Image Annotation, Data Annotation, Media annotation, AI annotation Checks feasibility of software prototypes Modifies code to fix errors Mansys Infotech Pvt Ltd. VLSI ... - 2021 Feb 24
Engineering Python
Vasant Nagar, Karnataka, India
... in Electronics and Communication Engineering,2020 CGPA: 7.17 PPK SC PU COLLEGE, ANKOLA PUC,PCMB,2016 Percentage:90.33 JAYCEE ENGLISH MEDIUM HIGH SCHOOL,AVERSA SSLC, 2014 Percentage:89.92 SKILLS: Programming Language: C, Python,SQL,Hdl, Verilog, ALP. ... - 2021 Feb 23
... in Electronics and Communication Engineering,2020 CGPA: 7.17 PPK SC PU COLLEGE, ANKOLA PUC,PCMB,2016 Percentage:90.33 JAYCEE ENGLISH MEDIUM HIGH SCHOOL,AVERSA SSLC, 2014 Percentage:89.92 SKILLS: Programming Language: C, Python,SQL,Hdl, Verilog, ALP. ... - 2021 Feb 23
Engineer Design
Vasant Nagar, Karnataka, India
... TECHNICAL SKILLS HDLs : Verilog. HVL : Methodology : System verilog, UVM Programming Languages : C, C++(basics) Platforms : Windows, Linux (basics) Simulators : Aldec riviera pro, iverilog. Other Skills: Static timing analysis (STA), Debugging, RTL ... - 2021 Feb 21
... TECHNICAL SKILLS HDLs : Verilog. HVL : Methodology : System verilog, UVM Programming Languages : C, C++(basics) Platforms : Windows, Linux (basics) Simulators : Aldec riviera pro, iverilog. Other Skills: Static timing analysis (STA), Debugging, RTL ... - 2021 Feb 21
Software Engineering
Vasant Nagar, Karnataka, India
... Software Languages: VHDL, VERILOG Software tools: Micro Wind, Xilinx, Keil, Cadence Virtuoso, Cadence Encounter, NC launch, Genus synthesis, MATLAB(Basics) Package: MS Office (Word, Powerpoint, Excel) Operating systems: Windows, XP, 7, 8, 10 ... - 2021 Feb 21
... Software Languages: VHDL, VERILOG Software tools: Micro Wind, Xilinx, Keil, Cadence Virtuoso, Cadence Encounter, NC launch, Genus synthesis, MATLAB(Basics) Package: MS Office (Word, Powerpoint, Excel) Operating systems: Windows, XP, 7, 8, 10 ... - 2021 Feb 21
Project Power
Bangalore, Karnataka, India
... Programming language known – Database, SQL,Verilog,Embedded C, ARM, C Worked on 8051 microcontroller, LPC2148, GSM and GPS modem. Tools used – Cadence, Xilinx Vivado. Operating system used – Windows and Ubuntu. Strengths Leadership qualities ... - 2021 Feb 18
... Programming language known – Database, SQL,Verilog,Embedded C, ARM, C Worked on 8051 microcontroller, LPC2148, GSM and GPS modem. Tools used – Cadence, Xilinx Vivado. Operating system used – Windows and Ubuntu. Strengths Leadership qualities ... - 2021 Feb 18