Aruna K

admcvi@r.postjobfree.com

+91-948*******,797-***-****

Professional Summary:

Total years of experience: 2+

• Currently working in the area of artificial intelligence and machine learning.

• Worked on compiler development for DNN models to executable generation for an ASIC AI/ML Chip using some frameworks, such as, Tensorfow, ONNX, MLIR, LLVM.

• Familiar with Python, C/C++, Conventional Machine Learning, Deep Learning, Natural Language Processing

Professional Skills:

Operating Systems Windows, Ubuntu.

Programming Languages C, C++, Python, Shell Scripting HDL /HVL Languages Verilog

Mathematical Tools MATLAB

Assembly Programming P8085, C8051, ARM, Rasberry PI EDA Tools

Cadence (nclaunch, imc, virtuoso), Keil, LT spice, Xil- inx Vivado

Hardware Accelerator Platforms FPGA (Altera), Xilinx Deep Learning Frameworks Tensorflow, PyTorch, Keras Compiler Development Tools

• ONNX for model interoperability

• MLIR for Intermediate Representation and

optimization

• LLVM for code generation (CPU or Special ISA)

ML Libraries

• SciKit-Learn

• Data Structures Manipulation: Pandas, NumPy

• Data Visualization Libraries: Matplotlib, Seaborn EXPERIENCE:

• Currently Working at Blueberry Semiconductors Pvt Ltd from Feb 2019 till Now. Project Details:

Project 1:

Title: Compiler Development MNC Client, USA

Description:

This project involves development of a tools eco-system (compiler, assembler, and runtime) for ASIC chip manufacturer.

The project involves:

• Model development using TensorFlow

• ONNX - Compiler front-end development

• IR Representation using MLIR

• LLVM – Code Generation

ONNX based front-end to interface Tensor Flow

• Directed Acyclic Graph (DAG) extraction for different DNN models

• Use Netron for model visualization

• Use protobuf compiler for conversion of to other file formats MLIR based intermediate representation

• This has 2 levels of IR – High Level and Low Level

• The HLIR is used to expand the nodes of the DNN model’s DAG for operations

• Conduct optimizations – Operator fusion, data layout, etc. LLVM based back-end for code generation for different hardware

• Lowering of MLIR output into LLVM

• Generation LLVM IR (Linear IR)

• Writing LLVM passes to optimize the code.

Generation of code for CPU.

Roles and Responsibilities:

• Modeled CNN, RNN and Fully connected networks using Tensorflow and Keras.

• Converted Tensorflow models to ONNX.

• Lowered ONNX model to MLIR and then to LLVM and generate the executable to run on the hardware.

Project 2:

Title: Drone Fleet Management System

Language Used: HTML, Python, Javascript

Roles and Responsibilities:

• Developed front end using HTML, Javascript.

• Used python and flask for the backend.

• Implemented airslot algorithm to provide airslots for the drones.

• Implemented obstacle detection algorithm for drone. Project 3:

Title: GPIO and UART library for device driver for a MNC client Language Used: C++

Roles and Responsibilities:

• Class implementation.

• Implemented factory, proxy, observer design patterns and C++ templates.

• Used UML design use cases.

Project 4:

Title: AI based Smart Resume Screening for a Singapore based recruitment company Language Used: Python, Javascript, HTML

Roles and Responsibilities:

• Setting up of MongoDB database for storing and retrieving Candidate’s data.

• Used Flask and AJAX call to integrate data visualization screens with database.

• Used NLP algorithms to process the JSON resume.

Project 5:

Title: Face detection and recognition using OpenCV and cascade classifiers for a Indian retail giant

Language Used: Python

Roles and Responsibilities:

• Detect the face and extract the features using landmarks detection.

• Compare the features of multiple faces with detected face in an image and recognize the particular face using cosine similarity. M.Tech Final Year Project

Title: “CMOS Down Conversion Mixer for Microwave Transceivers” Down conversion mixer is implemented in 0.18um CMOS technology. The mixer parameters are RF=3-10GHz, VDD=1.8V, IF=100MHz for RF=5.8GHz.The mixer is having conversion gain of 1.85dB,third order input intercept point of 14.5dBm and power dissipation of 8mW.The mixer is designed based on the folded Gilbert Cell architecture. BE Final Year Project

Title: “Raspberry Pi and ZigBee based Remote Area Communication” The remote areas are facing a major problem in communicating with external world especially during emergency condition. The objective of this project is to provide internet access to the remote areas by using ZigBee and Raspberry Pi.

Activities:

Participated in internship programme organized by VTU Bosch Rexorth Centre of Competence, Mysuru.

Presented a technical paper on “Raspberry Pi and ZigBee based Remote Area Communication” at International Conference organized by Coorg Institute of Technology.

Attended workshop on analog FPGA flow, digital FPGA flow and code coverage in cadence tool.

Completed Udemy online course on Tensorflow2.0: Deep Learning and Artificial Intelligence. EDUCATIONAL QUALIFICATION:

• M.Tech. (VLSI Design & Embedded System) from Visvesvaraya Technological University, Belagavi, 2019

• B.E. (Electronics & Communication) from Visvesvaraya Technological University, Belagavi, 2017 PERSONAL PROFILE:

• DOB :20-05-1996

• Address : Flat No.305,Golden Bell Appartment,#9,1st main,4th cross, Sharadambanagar,MES Ring Road, Bengaluru-13

• Linkedin Profile :https://www.linkedin.com/in/aruna-k-55a22b127/

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