| Resume alert | Resumes 1 - 10 of 134 |
Engineering Inplant Training
Visakhapatnam, AP, India
... Basics in programming language such as C, mplab,verilog. Areas of intriest : Analog and digital communication, Electronic circuits. Inplant Training: 1. Company Name : BSNL, Vizinagaram, Andhra Pradesh. Duration : two weeks Area of training : Basic ... - 2018 May 08
... Basics in programming language such as C, mplab,verilog. Areas of intriest : Analog and digital communication, Electronic circuits. Inplant Training: 1. Company Name : BSNL, Vizinagaram, Andhra Pradesh. Duration : two weeks Area of training : Basic ... - 2018 May 08
Power Plant Information Technology
AP, 531055, India
... RISC Stored program machine using verilog progrming. Skills : Technical skills : Proficient in RTL design and simulation. Good in VHDL, Verilog HDL programing language. Knowledge in ASIC front end &back end design. Computer skills : Windows,linux Os ... - 2018 Mar 28
... RISC Stored program machine using verilog progrming. Skills : Technical skills : Proficient in RTL design and simulation. Good in VHDL, Verilog HDL programing language. Knowledge in ASIC front end &back end design. Computer skills : Windows,linux Os ... - 2018 Mar 28
Software Manual Testing
Tirupati, AP, India
... Board of Secondary Education 2010 83% PROJECT Project Name: VLSI Implementation 0f a High Speed Single Precision Floating Point Unit Using Verilog. Description: Our Project deals with high speed operation for arithmetic expression and improve ... - 2018 Mar 14
... Board of Secondary Education 2010 83% PROJECT Project Name: VLSI Implementation 0f a High Speed Single Precision Floating Point Unit Using Verilog. Description: Our Project deals with high speed operation for arithmetic expression and improve ... - 2018 Mar 14
Design Engineer
AP, India
... TECHNICAL SKILLS Programming Languages: Verilog, SystemVerilog and C. Tools: Cadence OrCAD Schematic and PCB Design tools, Xilinx ISE Design9.1, VCS, Cadence EDA Tools (IUS & RTL Compiler). ACADEMIC PROJECTS CVC Projects: 1. Design and Verification ... - 2017 Dec 27
... TECHNICAL SKILLS Programming Languages: Verilog, SystemVerilog and C. Tools: Cadence OrCAD Schematic and PCB Design tools, Xilinx ISE Design9.1, VCS, Cadence EDA Tools (IUS & RTL Compiler). ACADEMIC PROJECTS CVC Projects: 1. Design and Verification ... - 2017 Dec 27
Project Design
Ambavaram, AP, 523112, India
... Svj college, porumamilla,kadapa Board of Intermediate Education, AP 2011 81.5% SSC Vijaya high School, Porumamilla,kadapa Board of Secondary Education, AP 2009 80% Technical skills: Programming Languages : C,Verilog,System verilog,uvm methodologies. ... - 2016 Dec 09
... Svj college, porumamilla,kadapa Board of Intermediate Education, AP 2011 81.5% SSC Vijaya high School, Porumamilla,kadapa Board of Secondary Education, AP 2009 80% Technical skills: Programming Languages : C,Verilog,System verilog,uvm methodologies. ... - 2016 Dec 09
Team Leader Project
AP, 523316, India
... leader) Status : had given presentation and report at KL UNIVERSITY Project Title :" DESIGN AND IMPLEMENTATION OF LOW POWER SEQUENCE DETECTOR using HDL(verilog)" Team role :Single(Team leader) Status : good Personal Memorandum: Father’s name : R. ... - 2016 Nov 10
... leader) Status : had given presentation and report at KL UNIVERSITY Project Title :" DESIGN AND IMPLEMENTATION OF LOW POWER SEQUENCE DETECTOR using HDL(verilog)" Team role :Single(Team leader) Status : good Personal Memorandum: Father’s name : R. ... - 2016 Nov 10
Project Design
AP, 520001, India
... Science) Manipal Academy of Higher Education (MAHE), Manipal 2016 Cgp 7.49 Technical Skills Language: C, System Verilog, Verilog EDA Tool: Cadence Virtuoso, RTL Compiler, NCSIM Operating System: Windows, LINUX Red Hat Academic Projects 1) ... - 2016 Sep 20
... Science) Manipal Academy of Higher Education (MAHE), Manipal 2016 Cgp 7.49 Technical Skills Language: C, System Verilog, Verilog EDA Tool: Cadence Virtuoso, RTL Compiler, NCSIM Operating System: Windows, LINUX Red Hat Academic Projects 1) ... - 2016 Sep 20
Project Power
Machilipatnam, AP, India
... Key Skills: C, TCL, Verilog, VHDL, ASIC, Physical Design, Floor Planning, Power Planning, CTS, DRC, STA, LVS. Cadence Tools : 1. SOC Encounter - for Place and Route 2. ETS - for Static Timing Analysis 3. RTL Compiler - for Logic Synthesis 4. ... - 2016 May 30
... Key Skills: C, TCL, Verilog, VHDL, ASIC, Physical Design, Floor Planning, Power Planning, CTS, DRC, STA, LVS. Cadence Tools : 1. SOC Encounter - for Place and Route 2. ETS - for Static Timing Analysis 3. RTL Compiler - for Logic Synthesis 4. ... - 2016 May 30
Project Health Care
Vuyyuru, AP, 521165, India
... 73.5 2004-2005 EDA Tools: • Hardware Description Language: VHDL, Verilog, System Verilog • Simulator: ModelSim6.4a, Xilinx ISim12.3, Matlab System Generator • Synthesizer: Leonardo Spectrum, Xilinx12.3 • CMOS Designing Tool: Micro wind Skills: • ... - 2016 Jan 26
... 73.5 2004-2005 EDA Tools: • Hardware Description Language: VHDL, Verilog, System Verilog • Simulator: ModelSim6.4a, Xilinx ISim12.3, Matlab System Generator • Synthesizer: Leonardo Spectrum, Xilinx12.3 • CMOS Designing Tool: Micro wind Skills: • ... - 2016 Jan 26
M.tech (Vlsi design)
AP, India
... 2007-2008 82.66% Computer Skill Set Languages : C programming, Verilog HDL, PERL Script, TCL script, VHDL Electronic Packages : SOC encounter, Cadence NC launch, Cadence Virtuoso, Altera (Quartus II), Model SIM PROFESSIONAL EXPERIENCE: IN-plant ... - 2015 Dec 08
... 2007-2008 82.66% Computer Skill Set Languages : C programming, Verilog HDL, PERL Script, TCL script, VHDL Electronic Packages : SOC encounter, Cadence NC launch, Cadence Virtuoso, Altera (Quartus II), Model SIM PROFESSIONAL EXPERIENCE: IN-plant ... - 2015 Dec 08