Design Engineer

S DURGAVANI

Email: ac3tmi@r.postjobfree.com Mob: +91-733*******

CAREER OBJECTIVE

To have a working experience with excellent team of professionally managed organization, which will enhance my logical and technical skills.

PROFESSIONAL EXPERIENCE

Worked as intern in Micro Solutions Pvt. Ltd. For PCB circuit design and layout.

ASIC Design Verification Engineer - Trainee in CVC Pvt. Ltd., Bangalore. ACADEMIC PROFILE

B.Tech in Electronics and Communication Engineering from Bhoj Reddy Engineering College for Women (JNTUH) with 60.4% in 2006-09.

Diploma in Electronics and Communication Engineering from Kamala Nehru Polytechnic for Women (SBTET) with 62.96% in 2006.

SSC from Board of secondary Education with 77.76% in 2002. TECHNICAL SKILLS

Programming Languages: Verilog, SystemVerilog and C.

Tools: Cadence OrCAD Schematic and PCB Design tools, Xilinx ISE Design9.1, VCS, Cadence EDA Tools (IUS & RTL Compiler).

ACADEMIC PROJECTS

CVC Projects:

1. Design and Verification of AMBA-APB Interface Protocol. Tools Used: Mpsim and Xilinx ISE.

Language Used: SystemVerilog

Methodology: UVM

Description: The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture (AMBA) hierarchy of buses and is optimized for minimal power consumption and reduced interface complexity. The RTL description is written using SystemVerilog, and design is simulated and verified using UVM.

2. Design of Synchronous FIFO

Tools Used: MPSim

Language Used: Verilog HDL, SystemVerilog

Description: FIFO is a First-In-First-Out memory queue with control logic that manages the read and writes operations, generates status flags, and provides optional handshake signals for interfacing with the user logic. The RTL description for the FIFO is written using Verilog HDL and SystemVerilog, and design is simulated in MPSim.

3. Design of Booth Algorithm for both signed and unsigned bit multiplication. Tools Used: ModelSim

Language Used: Verilog HDL

Description: The booth’s algorithm is the most frequently used method for multiplication. This algorithm allows the reduction in number of partial products to be compressed in the addition. Thus the compression speed can be enhanced. In this project a multiplier, using Booth’s multiplication algorithm is developed using Verilog HDL, and design is simulated in ModelSim. B.Tech

Title : Generation of Arbitrary Waveforms for Radar Applications. Environment : VHDL

Description : “Generation of Arbitrary Waveforms for Radar Applications” explains about the different types of arbitrary waveforms generated which are used for radar applications and in many military appliances. The total project is implemented on a hardware kit of virtex4 FPGA using VHDL programming language.

CURRICULUM ACTIVITES

Attended the Workshop Organized by Institute of Silicon Systems on VLSI ASIC Design using CADENCE Tools.

Attended the Workshop Organized by CVR College of Engineering on Semi-Custom Design Flow using CADENCE Tools.

Attended the Joint Workshop Organized by JNTU, Mentor Graphics Corp., & Trident Tec labs on VLSI Design Methodology using Mentor graphics Tools.

DECLARATION

I hereby declare that the facts mentioned above are true to the best of my belief and knowledge. Date :

Place : Hyderabad (DURGAVANI S)

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