Project Design

RESUME

MOHAMMAD HASSANBAIG

LG **, Academic Block 5, MIT Campus Ph no: +91-851*******

Manipal University, Manipal-576104 +91-741*******

Karnataka, India Email ID: *******@*****.***

Objective

Seeking a challenging position in the field of PHYSICAL Design, VLSI Design and Verification where I can enhance my knowledge and from my academic learning give my best to the organization.

Educational qualification

Class/Course

Name of Institute

Board/University

Year of Passing

Marks%

Matriculation

Z.P.H school of punadipadu

Board of Secondary Education

2007

66

Intermediate (10+2)

( Mathematics, Physics, Chemistry)

NARYANA junior college

Board of Intermediate, Andhra Pradesh

2009

67

B.TECH

(ELECTRONICS AND COMMUNICATION)

NIMRA college of Engineering and technology

JNTU Technical University kakinada

2013

61

MSc Tech

( VLSI)

SOIS (School of Information Science)

Manipal Academy of Higher Education (MAHE), Manipal

2016

Cgp 7.49

Technical Skills

Language: C, System Verilog, Verilog

EDA Tool: Cadence Virtuoso, RTL Compiler, NCSIM

Operating System: Windows, LINUX Red Hat

Academic Projects

1) Design and Implementation of AXI4 Master using System Verilog

Objective: The goal of the project is to design and implement Read/Write operation for

AMBA AXI4 bus in System Verilog.

Software: Incisive Tool Set

Description:

A mini project was done as a part of 2nd semester MS curriculum. The need for higher performance applications is driving the requirement for a new age of on-chip communication infrastructure. The goal of the project is to design and implement Read/Write operation for AMBA AXI4 bus in System Verilog using NCSim Simulator. This project examines the advantages of the new AMBA4 Advanced Extensible Interface 4(AXI4) master for on-chip bus infrastructure.

2) Design of 16-bit adders using an optimized Full adder

Objective: The goal of the project is to implement 16-bit carry save adder, carry select

adder and carry ripple adder using an optimized CMOS full adder.

Tool: Cadence virtuoso

Description:

Consideration of 9 Boolean expression to implement a 1-bit full adder circuit. These

Boolean logic realization and performances are analyzed in terms of transistor could delay

And power dissipation. From this analysis the optimized equation is selected and it is used

to implement the adder topologies. It is observed that adder designed with XOR and MUX

has the least delay, transistor count and power dissipation when compared to other combinations of gate.

3) Radar Detector using Microcontroller AT89C51

Team Size: 4

Description:

The radar operation is mainly dependent on the microcontroller and sensors and buzzer. Mainly buzzer used to alerting purpose, the main application of this project is to give protection for solders from the air attacks.

Areas of field interest

Digital design, Digital CMOS Design, Analog layout, Verification, any software, hardware and Physical Design

Hobbies

Music, Gardening, Playing indoor games

Extra-curricular

Organized events in college

Personal profile

Father’s Name : RAHIMANBAIG

Date of Birth : 20-12-1991

Sex : Male

Languages Known : English, Hindi, and Telugu

Nationality : Indian

Permanent Address : D/n 2/36-1, Masjid Street, kankipadu 521151, Andhra

Pradesh

Declaration

I hereby declare that the information furnished above is true to the best of my knowledge.

Place:

Date : MOHAMMAD HASSANBAIG

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