| Resume alert | Resumes 101 - 110 of 565 |
Technical Writer
San Jose, CA
... Engineer Cirrus Logic ● Senior Design Engineer SOTA Technology ● Design Engineer Singer-Link Flight Simulation PATENTS ● Patent – Two Factor Authentication Using Gesturing with a Touch Fingerprint Sensor ● Patent – Enhanced Pre-Boot Authentication ... - 2020 Feb 06
... Engineer Cirrus Logic ● Senior Design Engineer SOTA Technology ● Design Engineer Singer-Link Flight Simulation PATENTS ● Patent – Two Factor Authentication Using Gesturing with a Touch Fingerprint Sensor ● Patent – Enhanced Pre-Boot Authentication ... - 2020 Feb 06
Manager Software
San Jose, CA
... - Maintain corporate Patent/Trademark records and track Patent application process status. - Reported directly to the Head of Legal Affairs of the company. EMC Corporation, Santa Clara, CA, Technology Contracts Analyst Feb 2016 – Mar 2017 - Primary ... - 2020 Feb 04
... - Maintain corporate Patent/Trademark records and track Patent application process status. - Reported directly to the Head of Legal Affairs of the company. EMC Corporation, Santa Clara, CA, Technology Contracts Analyst Feb 2016 – Mar 2017 - Primary ... - 2020 Feb 04
Manager Security
San Jose, CA
... INDIA PATENT 1) HIGH AVAILABILITY FOR DISTRIBUTED NETWORK SERVICES IN AN EXTENDED BRIDGE - US10284389B2 2) DISTRIBUTED SECURITY RULE PROVISIONING IN AN EXTENDED BRIDGE - US10193706B2 3) INTELLIGENT, LOAD ADAPTIVE, AND SELF OPTIMIZING MASTER NODE ... - 2019 Dec 02
... INDIA PATENT 1) HIGH AVAILABILITY FOR DISTRIBUTED NETWORK SERVICES IN AN EXTENDED BRIDGE - US10284389B2 2) DISTRIBUTED SECURITY RULE PROVISIONING IN AN EXTENDED BRIDGE - US10193706B2 3) INTELLIGENT, LOAD ADAPTIVE, AND SELF OPTIMIZING MASTER NODE ... - 2019 Dec 02
Software Engineer Electrical Engineering
San Jose, CA
... PATENT / AWARDS United States Patent # 7,051,310, May 23, 2006 "Two-Stage Clock Tree Synthesis With Buffer Distribution Balancing" C Code for Bounded-Skew Clock Routing in VLSI, UCLA Case#. LA 97-088-01 R&D Special Achievement Award, Cadence Design ... - 2019 Sep 21
... PATENT / AWARDS United States Patent # 7,051,310, May 23, 2006 "Two-Stage Clock Tree Synthesis With Buffer Distribution Balancing" C Code for Bounded-Skew Clock Routing in VLSI, UCLA Case#. LA 97-088-01 R&D Special Achievement Award, Cadence Design ... - 2019 Sep 21
Software Engineer Developer
San Jose, CA
... Track most viewed products using relational databases • Integrated product catalogs from other web applications using networking protocols and distributed systems • Implementation of a mail client using SMTP protocol Developed front-end for patent ... - 2019 Sep 13
... Track most viewed products using relational databases • Integrated product catalogs from other web applications using networking protocols and distributed systems • Implementation of a mail client using SMTP protocol Developed front-end for patent ... - 2019 Sep 13
Engineer Software
Fremont, CA
... PATENT 01/2003, U.S. patent 6507940 granted, for the method of generating image information for a window view from IC layout-format (GDS) data. TRAININGS Solaris 2.X System Administration. Linux Administrator. CCNA Networking Basics. - 2019 May 17
... PATENT 01/2003, U.S. patent 6507940 granted, for the method of generating image information for a window view from IC layout-format (GDS) data. TRAININGS Solaris 2.X System Administration. Linux Administrator. CCNA Networking Basics. - 2019 May 17
Design Engineer Engineering
San Jose, CA, 95125
... Laser submarine optical detection system patent application. US Navy. ARM Cortex A 9 IoT c++ QR code demonstration. REST API Azure MQTT heroku Salesforce IBM Watson Bluemix node-red arm mbed-os RTOS 5.x Cloud connectivity REST API SOAP. 2015-18 US ... - 2019 Apr 28
... Laser submarine optical detection system patent application. US Navy. ARM Cortex A 9 IoT c++ QR code demonstration. REST API Azure MQTT heroku Salesforce IBM Watson Bluemix node-red arm mbed-os RTOS 5.x Cloud connectivity REST API SOAP. 2015-18 US ... - 2019 Apr 28
Wireless Modem Systems Engineer
Mountain View, CA
... Worked on ASUS Project as a joint inventor of a D2D application and a patent co-author, providing potential ideas/technologies for ASUS wireless department. Proposed a method determining whether to performing a D2D transmission and a cellular ... - 2019 Apr 18
... Worked on ASUS Project as a joint inventor of a D2D application and a patent co-author, providing potential ideas/technologies for ASUS wireless department. Proposed a method determining whether to performing a D2D transmission and a cellular ... - 2019 Apr 18
Sales Customer Service
Scotts Valley, CA
... Patent 20,070,128,351, 7 October 2004. HONORS First place 2003 Roon Award Competition Paper, Federation of Societies for Coatings Technology, ICE convention, October 2003, Philadelphia, PA PUBLICATIONS “Mg-Rich Coatings: A New Paradigm for Cr-Free ... - 2019 Mar 29
... Patent 20,070,128,351, 7 October 2004. HONORS First place 2003 Roon Award Competition Paper, Federation of Societies for Coatings Technology, ICE convention, October 2003, Philadelphia, PA PUBLICATIONS “Mg-Rich Coatings: A New Paradigm for Cr-Free ... - 2019 Mar 29
Electrical Engineer
San Jose, CA
... Patent Issued: 6,616,014 Point of Use Precision liquid mixing apparatus and method. A system apparatus and method providing a consistent liquid mixture according to a programmable recipe at a point of use. U.S. Patent is pending: Cable spool ... - 2019 Mar 11
... Patent Issued: 6,616,014 Point of Use Precision liquid mixing apparatus and method. A system apparatus and method providing a consistent liquid mixture according to a programmable recipe at a point of use. U.S. Patent is pending: Cable spool ... - 2019 Mar 11