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Entry-Level Design Verification Engineer (UVM/SystemVerilog) resume in Vijayanagar, Karnataka, 560040, India - December 2025

Rashmi R

Bengaluru +91-636******* ************@*****.***

Profile Summary

Design Verification Engineer skilled in SystemVerilog, UVM, and AMBA APB protocol verification. Completed 6-month training at ChipEdge Technologies, Bengaluru. Experienced in building UVM testbenches, developing drivers,...


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