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Design Engineer Controller resume in San Jose, CA - May 2023

Elbert Shiang

Palo Alto, CA ************@*****.*** 408-***-****

SUMMARY

Accomplished 6 ASICs and 10 FPGAs from functional specification to the final production.

Experienced in Digital and Mixed-Signal SOC design including chip architecture, RTL implementation, RTL synthesis, ASIC...


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