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Engineer Design resume in San Jose, CA - March 2017
JAGANNATHAN RADHAKRISHNAN
(R) 408-***-**** (C) 408-***-**** aczbto@r.postjobfree.com
Experienced Verification/Designer of ASIC/FPGA, SOC for telecom and computer industries.
SUMMARY OF QUALIFICATIONS
Over 15 years of System design, SOC, ASIC/FPGA design, Modeling and Verification background....
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