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Verilog, system verilog, uvm resume in Bengaluru, KA, 560001, India - April 2016
VIJAYA LAKSHMI K
Porumamilla, KADAPA, Email: ********@*****.***
A.P, India – 516505 Mobile: +918*********
Summary of Qualifications:
Good understanding of the ASIC and FPGA design flow
Experience in writing test benches in SystemVerilog and UVM
Very good knowledge...
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