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Test Cases Design resume in Hyderabad, Telangana, India - March 2016
A.Ramakrishna Reddy email: act15m@r.postjobfree.com Mob:949*******
AIM:
Looking for a senior level VLSI ASIC/SOC/IP Verification lead position, to play a role of individual contributor and/or technical leadership.
SUMMARY:
Having 12 Years of relevant experience with Verilog, SystemVerilog, OVM...
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