Test Cases Design

A.Ramakrishna Reddy email: ********@*******.*** Mob:949*******

AIM:

Looking for a senior level VLSI ASIC/SOC/IP Verification lead position, to play a role of individual contributor and/or technical leadership.

SUMMARY:

Having 12 Years of relevant experience with Verilog, SystemVerilog, OVM & UVM based ASIC/SOC/IP Verification.

oExtensively worked on implementing Bus functional models involving USB1.1, USB2.0, USB3.0, HDCP protocols, and hands on experience with SATA, PCIE, SP, PP protocols

oReceived Professional Excellence Award in 2007, from MOCHIP Semiconductor Technology Ltd, for the work done over the production Test vectors of MCS9735.

oExpertise in Verification Architectural Design & Development of the functional behavioral models for a) USB11 HUB BFM with serial Phy interface, b) USB11 Device BFM with serial Phy interface, c) USB11 Host controller BFM with serial Phy interface, d) USB20 Host controller BFM with serial Phy interface, e) USB20 OTG BFM with UTMI interface, f) HDMI-HDCP Model, g) USB2.0 Host BFM with UTMI interface, i) USB2.0 Device BFM with UTMI interface & j) PCIe to Display Controller application model.

oExpertise in Functional Production Test vector Development & Functional Code coverage metric analysis over the multiple projects of MCS7710/11/15/20, MCS7780/7784, MCS7830, MCS9735, MCS9950, etc.

oExpertise in RTL Functional, Gate level & PnR Verification.

oHands on exposure in ASIC-RTL Design & development of OHCI Master operational block & HDMI-Rx-HDCP authentication blocks.

oSuccessfully completed full-cycle Chip level verification for 10 ASICs.

oWorking with multi-site verification teams

SKILLS:

oVerification Languages: Verilog, SystemVerilog, C++

oVerification Methodologies: OVM, UVM

oEDA Tools: Questasim, VCS, NC-SIM, SILOS-III, Verdi.

oHardware Architectures: USB1.1, USB2.0, USB OTG, USB3.0, SATA, HDCP, PCie, Serial port, Parallel port.

EXPERIANCE:

Presently working with Wipro Technologies, as a Verification Architect(April 2014 to till date)

oWorking on the 'Serial Subsystem & PCIe Subsystem' level verification of the SATA Physical layer (PCS & PMA) for the MicroSemi G5 project.

Responsibilities: My work involved verification of SATA Pipe for Host & Device in System Verilog & UVM.

Involved in Functional verification and validation of the SATA Serial VIP for Host & Device functionality and functional coverage analysis in in System Verilog & UVM.

Involved in Functional verification and validation of the SATA PIPE MAC VIP for Host & Device functionality and functional coverage analysis in in System Verilog & UVM.

Involved in Functional Test plan and Testbench development for the SATA Host & Device for the G5 project.

Involved in writing functional test cases in UVM for SATA Host & Device modes of Gen1, Gen2 & Gen3 speeds.

Involved in Functional coverage development for SATA Host & Device and RTL.

Involved in running regression and debugging the failures and Functional coverage analysis

oWorked on ‘TMAN IP’ verification for Freescale Semiconductor. TMAN IP is a Freescale’s customized Timer management IP, working as a team member for the verification of TMAN IP by writing test cases in SV & UVM, added SV assertions for functional coverage, and also doing code coverage (toggle, FSM & Line) analysis.

oWorked on ‘B3421 SOC’ peripheral verification for Freescale Semiconductor, B3421 is a broadband wireless infrastructure based SOC, working with a team of 3 members for the verification of the peripherals (Skyblue, Magenta, SATA, USB, Timers by using SV & SVBCL\methodology.

oBroadcom Inc., Santa Clara, CA, as a consultant from MosChip

Worked on STS(Self-test Subsystem level) IP level verification of their KBP projects at Broadcom, involved in TB Verification infrastructure development, implemented and executed functional directed & random test cases with functional data & control oriented coverage in System Verilog

oAMD, Hyderabad as a Verification consultant from MosChip

Worked with AMD Hyderabad, as a team member of the GNB TD (Deterministic Testing), and Graphics IO (PCIe) Teams, my work involved in TD Verification of the GNB (Graphics North Bridge) and GIO Verification of SOC APU Chipset Projects

oNethra, Santa Clara, CA, as a Verification consultant from MosChip

Worked as a team member as part of the Nethra Verification team USA, my work involved in top level USB OTG peripheral verification of the for the H.264 encoder SOC project.

oVerification of USB3.0 Host IP : Worked as a verification lead for the USB3.0 Host controller IP, developed USB3.0 Host verification architecture & test plan documents and involved in Design & implementation of the xHCI host application model & USB3.0 Link layer OVC(with System Verilog & OVM).

oVerification of PCIe to Highspeed Serial parallel port & Display controller ASIC adapter : Worked as a Verification lead for the Rev-a & Rev-b MCS9900 ASIC (PCIe to Serial, parallel port & Display controller), developed verification architecture & test plan documents, developed verification environment, and also design & implementation of the PCIe to display controller & PCIe power management test cases for RTL, FPGA, Gate & PnR simulations.

oVerification of PCIe to USB & High speed serial, parallel port controller ASIC adapter: Responsible for the verification of MCS9900 ASIC, for RTL, FPGA, Gate-level & PnR simulations.

oVerification of MCS8140 SOC & MCS9000 ASIC : Responsible for the verification support of the MCS8140 SOC & MCS9000 ASIC over the up gradation & customization of the USB2.0 OTG, HOST & Device BFMs & functional testcases for RTL, Gate & PnR simulations.

oVerification of USB2.0 to High speed serial, parallel port controller ASIC adapter: Worked as a verification team member & FPGA validation of the USB2.0 to Serial & parallel port ASIC, and also responsible for the verification of RTL, FPGA, Gate-level & PnR simulations, and also developed functional production test vectors for USB2.0 to Serial & parallel port ASIC (for Wafer & Packages).

oVerification of USB2.0 OTG IP: Responsible for the verification of the USB2.0 OTG IP, for RTL, Gate-level simulations.

oVerification of USB to IrDa ASIC(MCS773X) adapter: Worked as a verification lead & responsible for verification Architecture, environment & testplan development, implementation and execution of functional testcases for FPFA, RTL, Gate level & PnR simulations, and also developed functional production testvectors for MCS773X ASIC(for Wafer & Packages).

oVerification of USB1.1 to serial port ASIC(MCS7715) adapter: Worked as a verification lead & responsible for verification Architecture, environment & testplan development, implementation and execution of functional testcases for FPFA, RTL, Gate level & PnR simulations, and also developed functional production test vectors for MCS7715 ASIC(for wafer & packages).

oVerification of USB1.1 to serial port ASIC(MCS7715) adapter : Architected MCS7700 ASIC (USB1.1 HUB) Verification Environment, and also developed test plan & verification documents.

oVerification of USB1.1 HUB ASIC(MCS7700) : Responsible for Design & implementation of USB1.1 Host & Device application BFMs, implementation and execution of functional test cases for FPFA, RTL, Gate level & PnR simulations, and also developed functional production test vectors for MCS7700 USB1.1 HUB ASIC(for wafer & packages).

oVerification of USB1.1 to Combo 3port Hub & serial, parallel ports ASIC(MCS77xx) adapter: Responsible for verification Architecture, environment & testplan development.

oDesigned & implemented USB1.1 Host Application BFM, USB1.1 Device BFM along with Serial & Parallel port applications, implementation and execution of functional test cases for FPFA, RTL, Gate level & PnR simulations, and also developed functional production test vectors for MCS77xxASIC(for wafer & packages).

oRTL Design & Verification of HDCP for HDMI TX & RX: RTL Designing of HDCP IP for HDMI TX & HDMI IP protocols and also developed HDCP verification IP for HDMI TX & HDMI RX protocols and verified the same.

oRTL Design & Verification of USB1.1 Host Master slave & DLL Block : RTL Designing of USB1.1 Host Master slave controllers block and developed host application models for the same and verified the same. Designed USB1.1 DLL Block and verified the same.

Educational Qualifications:

oMS (PR) from S.V University,

oM.Tech in ECE from Manav Bharati University.

oB.E. Electronics Engineering, Nagpur University.

oAdvanced Integrated Training in VLSI Design from ECIL (Sep 1999 – March 2000), Hyderabad.

oHonor’s Postgraduate Diploma in Computer Egg. & Technology, from IIHT Hyderabad.

Address for communication :

: Flat no: 12/104, Old Malahar Apartments, SAHARA STATES, L.B.Nager, Hyderabad, AP, INDIA-500068.

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