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Engineer Design resume in Irvine, CA - December 2013
Shanshan Xu
(cell)***/***-****
Email ********@*****.***
SPECIALTY Senior ASIC/FPGA design and pre-silicon/post-silicon
verification
engineer with 15+ years of experience in all
areas of an ASIC/FPGA
design cycle including system/chip-
architecture, block-level micro-
architecture,...
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