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Verilog, Perl, Digital IC design, FPGA/ASIC design, Physical Design resume in San Jose, CA - January 2018

Jiajia Wang

bonnet Ct, San Jose, CA***** ac3z50@r.postjobfree.com 972-***-****

OBJECTIVE

Seeking for Fulltime employment in the field of IC design, ASIC design, SRAM design and FPGA design stating immediately EDUCATION

• M.S, University of Texas at Dallas (UTD), Research Assistant Sep. 2014 –...


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