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Verilog, System Verilog, SV Assertions, Physical Design, DFT resume in Campbell, CA - January 2018
MANJUNATH EKANATH GUNAGI
*** ***** ******, *#***, Campbell, CA – 95008 Email: ac3xsp@r.postjobfree.com Phone: 937-***-**** OBJECTIVE
Seeking an entry level full-time opportunity in the field of FPGA/ASIC Design and Verification, Physical Design, DFT. SKILLS
• Programming Languages : Proficiency...
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